Nehalem

Intel's Nehalem Microprocessor Architecture Explained

1. NEHALEM Innovative Micro architecture From Intel

2. What is Micro architecture? Microarchitecture   (µarch or uarch), is the way a given ISA is implemented on a processor. Micro architecture design focus on these aspects Chip area/cost Power consumption Logic complexity Ease of connectivity Manufacturability Ease of debugging Testability

3. Nehalem ? Is the codename for thelatest  Intel  processor micro architecture. The first processor released with the Nehalem architecture was the desktop Core i7 (Nov 2008). It was then followed by several Xeon processors and by i3 and i5. Was supposed to be latest evolution of NetBurst, but was renamed as ‘Nehalem’ HT is reintroduced along with an L3 cache to achieve higher clock speeds and energy efficiency.

4. Technology Wide range of two, four, six, eight, ten or twelve core processors. Initial release with 45nm manufacturing process, followed by 32nm variants.It allows more number of transistors in a single die (731 million in quad core variant!). Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2  channel. Integrated graphics processor (IGP) located off-die, but in the same CPU package.

5. Technology (.. contd ) A new point-to-point processor interconnect, the Intel QuickPath Interconnect, in high-end models, replacing the legacy  front side bus Integration of PCI Express and Direct Media Interface into the processor in mid-range models, replacing the  northbridge Simultaneous multithreading (Hyper Threading) by multiple cores which enables two threads per core. Native ( monolithic) quad- and octal-core processor. 33% more in-flight micro-operations  than Core 2 uarch.

6. Technology (.. contd ) The following caches : 32  KB L1 instruction and 32 KB L1 data cache per core 256 KB L2 cache per core 4–12 MB L3 cache (2MB/Core) shared by all cores Second-level  branch predictor  and second-level translation lookaside buffer. Modular blocks of components such as cores that can be added and subtracted for varying market segments.

7. Performance and Power Optimizations 1.1× to 1.25× the single-threaded performance or 1.2× to 2× the multithreaded performance at the same power level. 30% lower power usage for the same  performance According to a preview from  AnandTech  "expect a 20–30% overall advantage over Penryn with a 10% increase in power usage . Per Core, clock-for-clock, Nehalem provides a 15–20% increase in performance compared to Penryn

8. Processor Release Timeline The successor to  Nehalem  and  Westmere  will be  Sandy Bridge , scheduled for release in late 2010, according to statements by Intel. The successor to  Sandy Bridge  will be  Haswell , scheduled for release in 2012. It will come with a new cache subsystem, a FMA (fused multiply-add) unit, and a vector coprocessor.

9. Related Definitions (1/4) An  instruction set , or  instruction set architecture  (ISA) , is the part of the computer architecture related to  programming, including the native  data types, instructions ,  registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. ISA includes specifications of the set of opcodes (machine language), and the native commands implemented by a particular processor

10. Related Definitions (2/4) Per the International Technology Roadmap for Semiconductors, the  45 nm  technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. QuickPath is a core to core interconnection that eases inter processor data transfer with a bandwidth of 25.6GB/Second.

11. Related Definitions (3/4) Front side Bus is the the  bus that carries data between the CPU and the northbridge . Back side bus is the bus between CPU and cache memory.

12. Related Definitions (4/4) branch predictor  is a digital circuit that tries to guess which way a branch (e.g. an if-then-else structure) will go before this is known for sure.

13. Questions?

14. Thank You!