NMOSBICOMS.pptx it about semiconductors,

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1. N MOS Fabrication Process

2. N-MOS Fabrication Process Fig. (1) Pure Si single crystal Si-substrate Fig. (2) P-type impurity is lightly doped - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

3. N-MOS Fabrication Process Fig. (3) SiO 2 Deposited over si surface Fig. (4) Photoresist is deposited over SiO 2 layer Thick SiO 2 (1 µ m) Photoresist Thick SiO 2 (1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

4. N-MOS Fabrication Process Fig. (5) Photoresist layer is exposed to UV Light through a mask Photoresist Thick SiO 2 (1 µ m) UV Light Mask-1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask-1 is used to expose the SiO 2 where S, D and G is to be formed.

5. N-MOS Fabrication Process Fig. (6) Developer removes unpolymerised photoresist. It will cause no effect on Si surface Polymerised Photoresist Thick SiO 2 (1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

6. N-MOS Fabrication Process Fig. (7) Etching [HF acid is used] will remove SiO2 layer which is in direct contact with etching solution Thick SiO 2 (1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

7. N-MOS Fabrication Process Fig. (7) unpolymerised photoresist is also etched away [using H2SO4] Thick SiO 2 (1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

8. N-MOS Fabrication Process Fig. (8) A thin layer of SiO 2 grown over the entire chip surface Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

9. N-MOS Fabrication Process Fig. (9) A thin layer of polysilicon is grown over the entire chip surface to form GATE Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) Polysilicon layer (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

10. N-MOS Fabrication Process Fig. (10) A layer of photoresist is grown over polysilicon layer Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) Polysilicon layer Photoresist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

11. N-MOS Fabrication Process Fig. (11) Photoresist is exposed to UV Light UV Light Mask-2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask-2 is used to deposit Polysilicon to form gate.

12. N-MOS Fabrication Process Fig. (12) Etching will remove that portion of Thin SiO2 which is not exposed to UV light Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) Polysilicon - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13. N-MOS Fabrication Process Fig. (13) Polymerised photoresist is also stripped away Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) Polysilicon used as GATE (1 – 2 µm) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

14. N-MOS Fabrication Process Fig. (14) n + Doping to form SOURCE and DRAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) Thin SiO 2 (0.1 µ m) GATE - - - - - n+ - - - - - n+ SOURCE DRAIN

15. N-MOS Fabrication Process Step - Metallization Fig. (15) A thick layer of SiO2 (1 µm) is again grown. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m)

16. N-MOS Fabrication Process Step - Metallization Fig. (16) Photoresist is grown over thick SiO 2 . Selected areas of the poly GATE and SOURCE and DRAIN are exposed where contact cuts are to be made - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Photoresist Mask-3 UV Light Mask-3 is used to make contact cuts for S, D and G.

17. N-MOS Fabrication Process Step - Metallization Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised photoresist and SiO 2 below it are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Photoresist Mask-3

18. N-MOS Fabrication Process Step - Metallization Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Photoresist Mask-3

19. N-MOS Fabrication Process Step - Metallization Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Metal (1µm)

20. N-MOS Fabrication Process Step - Metallization Fig. (20) Photoresist is deposited over the metal. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Metal (1µm) Photoresist

21. N-MOS Fabrication Process Step - Metallization Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Metal (1µm) Photoresist UV Light Mask-4 Mask-4 is used to deposit metal in contact cuts of S, D and G.

22. N-MOS Fabrication Process Step - Metallization Fig. (22) Photoresist and metal which is not exposed to UV light are etched away. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO 2 (1 µ m) - - - - - n+ - - - - - n+ Thick SiO 2 (1 µ m) Metal (1µm) Photoresist Mask-4

23. N-MOS Fabrication Process Step - Metallization Fig. (23) Final n-MOS Transistor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - n+ - - - - - n+ SOURCE DRAIN GATE

24. Advantages of integrated circuits Miniaturization and hence increased equipment density. Cost reduction due to batch processing. Increased system reliability due to the elimination of soldered joints. Improved functional performance. Matched devices. Increased operating speeds. Reduction in power consumption

25. Why should we designers know about fabrication? Design performance varies after fab. Due to process variations- Dimensions vary due to shifting of masks, Dopants diffusing beneath the masks, Etching deffects Hence MOS parameters like g m , W, L, I D varies . So we have to design with margins.

26. Defective IC Individual integrated circuits are tested to distinguish good die from bad ones. n-well p-channel transistor p-well n-channel transistor p+ substrate bonding pad nitride Metal 2

27. Die Cut and Assembly Good chips are attached to a lead frame package.

28. Die Attach and Wire Bonding lead frame wire bonding pad connecting pin

29. Final Test Chips are electrically tested under varying environmental conditions.

30. FABRICATION OF BICMOS THROUGH N-WELL

31. NMOS PMOS G D S G D S NPN-BJT C B E N Plus Buried Layer N-Well (Collector) N-Diff N-Diff P-Diff P-Diff N-Plus Emitter P-SUBSTRATE P-EPITAXY BICMOS STRUCTURE

32. P-SUBSTRATE P-SUBSTRATE P-SUBSTRATE IS TAKEN P-TYPE SUBSTRATE IS COVERED WITH OXIDE LAYER

33. N Plus Buried Layer P-SUBSTRATE P-SUBSTRATE A WINDOW IS OPENED THROUGH OXIDE LAYER THROUGH THE WINDOW N TYPE IMPURITIES IS HEAVILY DOPED

34. N Plus Buried Layer P-SUBSTRATE P-EPITAXY P-EPITAXY LAYER IS GROWN ON THE ENTIRE SURFACE

35. N Plus Buried Layer P-SUBSTRATE P-EPITAXY THE ENTIRE SURFACE IS COVERED WITH OXIDE LAYER AND TWO WINDOWS ARE OPENED THROUGH THE OXIDE LAYER

36. N Plus Buried Layer N-Well (Collector) N-Well P-SUBSTRATE P-EPITAXY THROUGH THE TWO WINDOWS N-TYPE IMPURITIES ARE DIFFUSED TO FORM N-WELLS

37. N Plus Buried Layer N-Well (Collector) N-Well P-SUBSTRATE P-EPITAXY THREE WINDOWS ARE OPENED THROUGH THE OXIDE LAYER , IN THESE THREE WINDOWS THREE ACTIVE DEVICES NMOS,PMOS AND NPN BJT ARE FORMED

38. N Plus Buried Layer N-Well (Collector) N-Well P-SUBSTRATE P-EPITAXY THE ENTIRE SURFACE IS COVERED WITH THINOX AND POLYSILICON AND ARE PATTERNED TO FORM THE GATE TERMINALS OF THE NMOS AND PMOS

39. N Plus Buried Layer N-Well (Collector) N-Well P-Base P-SUBSTRATE P-EPITAXY THROUGH THE 3 RD WINDOW THE P-IMPURITIES ARE MODERATELY DOPED TO FORM THE BASE TERMINAL OF BJT N-WELL ACTS LIKE THE COLLECTOR TERMINAL

40. N Plus Buried Layer N-Well (Collector) N-Well P-Base P-SUBSTRATE P-EPITAXY N-Diff N-Diff N-Plus Emitter THE N-TYPE IMPURITES ARE HEAVILY DOPED TO FORM 1.SOURCE AND DRAIN REGION OF NMOS 2.EMITTER TERMINAL OF BJT 3.AND INTO NWELL COLLECTOR REGION FOR CONTACT PURPOSE

41. N Plus Buried Layer N-Well (Collector) N-Well N-Diff N-Diff P-Diff P-Diff P-Base N-Plus Emitter P-SUBSTRATE P-EPITAXY THE P-TYPE IMPURITES ARE HEAVILY DOPED TO FORM 1.SOURCE AND DRAIN REGION OF PMOS 2.AND INTO P-BASE REGION FOR CONTACT PURPOSE

42. N Plus Buried Layer N-Well (Collector) N-Well N-Diff N-Diff P-Diff P-Diff P-Base N-Plus Emitter P-SUBSTRATE P-EPITAXY THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER

43. N Plus Buried Layer N-Well (Collector) N-Well N-Diff N-Diff P-Diff P-Diff P-Base N-Plus Emitter P-SUBSTRATE P-EPITAXY THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER AND IS PATTERNED FOR CONTACT CUTS

44. NMOS PMOS G D S G D S NPN-BJT C B E N Plus Buried Layer N-Well (Collector) N-Diff N-Diff P-Diff P-Diff N-Plus Emitter P-SUBSTRATE P-EPITAXY METAL CONTACTS ARE FORMED

45. Thank you