Non Ideal Transistor Theory- Mosfet second order effects

MOSFET Non Ideal Effects

1. Lecture 4:
Nonideal
Transistor
Theory

2. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 2
Outline
Nonideal Transistor Behavior
–High Field Effects
•Mobility Degradation
•Velocity Saturation
–Channel Length Modulation
–Threshold Voltage Effects
•Body Effect
•Drain-Induced Barrier Lowering
•Short Channel Effect
–Leakage
•Subthreshold Leakage
•Gate Leakage
•Junction Leakage
Process and Environmental Variations

3. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 3
Ideal Transistor I-V
Shockley long-channel transistor models
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

 
    
 


 



4. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 4
Ideal vs. Simulated nMOS I-V Plot
65 nm IBM process, V
DD = 1.0 V
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (A)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

5. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 5
ON and OFF Current
I
on = I
ds @ V
gs = V
ds = V
DD
–Saturation
I
off = I
ds @ V
gs = 0, V
ds = V
DD
–Cutoff
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
Vds
Ids (A)
Vgs = 1.0
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Ion = 747 mA @
Vgs = Vds = VDD

6. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 6
Electric Fields Effects
Vertical electric field: E
vert
= V
gs
/ t
ox
–Attracts carriers into channel
–Long channel: Q
channel
proportional to E
vert
Lateral electric field: E
lat = V
ds / L
–Accelerates carriers from drain to source
–Long channel: v = μE
lat

7. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 7
Coffee Cart Analogy
Tired student runs from VLSI lab to coffee cart
Freshmen are pouring out of the physics lecture hall
V
ds
is how long you have been up
–Your velocity = fatigue × mobility
V
gs is a wind blowing you against the glass (SiO
2) wall
At high V
gs
, you are buffeted against the wall
–Mobility degradation
At high V
ds
, you scatter off freshmen, fall down, get up
–Velocity saturation
•Don’t confuse this with the saturation region

8. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 8
Mobility Degradation
High E
vert
effectively reduces mobility
–Collisions with oxide interface

9. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 9
Velocity Saturation
At high E
lat
, carrier velocity rolls off
–Carriers scatter off atoms in silicon lattice
–Velocity reaches v
sat
•Electrons: 10
7
cm/s
•Holes: 8 x 10
6
cm/s
–Better model

10. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 10
Vel Sat I-V Effects
Ideal transistor ON current increases with V
DD
2
Velocity-saturated ON current increases with V
DD
Real transistors are partially velocity saturated
–Approximate with α-power law model
–I
ds scales with V
DD
α

–1 < α < 2 determined empirically (≈ 1.3 for 65 nm)
 
 
2
2
ox
2 2
gs t
ds gs t
V VW
I C V V
L



  

11. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 11
-Power Model
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
V V
V
I I V V
V
I V V
 


 

 

 
 
/2
2
dsat c gs t
dsat v gs t
I P V V
V P V V



 
 

12. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 12
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
–Region between n and p with no carriers
–Width of depletion L
d
region grows with reverse bias
–L
eff
= L – L
d
Shorter L
eff
gives more current
–I
ds increases with V
ds
–Even in saturation
n
+
p
GateSource Drain
bulk Si
n
+
VDD
GND
VDD
GND
L
Leff
Depletion Region
Width: Ld

13. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 13
Chan Length Mod I-V
λ = channel length modulation coefficient
–not feature size
–Empirically fit to I-V characteristics
  
2
1
2
ds gs t ds
I V V V

  

14. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 14
Threshold Voltage Effects
V
t
is V
gs
for which the channel starts to invert
Ideal models assumed V
t is constant
Really depends (weakly) on almost everything else:
–Body voltage: Body Effect
–Drain voltage: Drain-Induced Barrier Lowering
–Channel length: Short Channel Effect

15. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 15
Body Effect
Body is a fourth transistor terminal
V
sb affects the charge required to invert the channel
– Increasing V
s or decreasing V
b increases V
t
V
t0 = nominal threshold voltage

s
= surface potential at threshold
–Depends on doping level N
A
–And intrinsic carrier concentration n
i
 γ = body effect coefficient
 0t t s sb s
V V V    
2 ln
A
s T
i
N
v
n

siox
si
ox ox
2q
2q
A
A
Nt
N
C

 

 

16. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 16
Body Effect Cont.
For small source-to-body voltage, treat as linear

17. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 17
DIBL
Electric field from drain affects channel
More pronounced in small transistors where the
drain is closer to the channel
Drain-Induced Barrier Lowering
–Drain voltage also affect V
t
High drain voltage causes current to increase.
t t ds
V V V 

18. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 18
Short Channel Effect
In small transistors, source/drain depletion regions
extend into the channel
–Impacts the amount of charge required to invert
the channel
–And thus makes V
t
a function of channel length
Short channel effect: V
t
increases with L
–Some processes exhibit a reverse short channel
effect in which V
t
decreases with L

19. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 19
Leakage
What about current in cutoff?
Simulated results
What differs?
–Current doesn’t
go to 0 in cutoff

20. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 20
Leakage Sources
Subthreshold conduction
–Transistors can’t abruptly turn ON or OFF
–Dominant source in contemporary transistors
Gate leakage
–Tunneling through ultrathin gate dielectric
Junction leakage
–Reverse-biased PN junction diode current

21. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 21
Subthreshold Leakage
Subthreshold leakage exponential with V
gs
n is process dependent
–typically 1.3-1.7
Rewrite relative to I
off on log scale
S ≈ 100 mV/decade @ room temperature
0
0
e 1 e
gs t ds sb ds
T T
V V V k V V
nv v
ds ds
I I

   
 
   
 
 

22. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 22
Gate Leakage
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to t
ox and V
DD
–A and B are tech constants
–Greater for electrons
•So nMOS gates leak more
Negligible for older processes (t
ox > 20 Å)
Critically important at 65 nm and below (t
ox ≈ 10.5 Å)
From [Song01]

23. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 23
Junction Leakage
Reverse-biased p-n junctions have some leakage
–Ordinary diode leakage
–Band-to-band tunneling (BTBT)
–Gate-induced drain leakage (GIDL)
n well
n+n+ n+p+p+p+
p substrate

24. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 24
Diode Leakage
Reverse-biased p-n junctions have some leakage
At any significant negative diode voltage, I
D
= -I
s
I
s depends on doping levels
–And area and perimeter of diffusion regions
–Typically < 1 fA/μm
2
(negligible)
e 1
D
T
V
v
D S
I I
 
  
 
 

25. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 25
Band-to-Band Tunneling
Tunneling across heavily doped p-n junctions
–Especially sidewall between drain & channel
when halo doping is used to increase V
t
Increases junction leakage to significant levels
–X
j
: sidewall junction depth
–E
g: bandgap voltage
–A, B: tech constants

26. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 26
Gate-Induced Drain Leakage
Occurs at overlap between gate and drain
–Most pronounced when drain is at V
DD, gate is at
a negative voltage
–Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

27. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 27
Temperature Sensitivity
Increasing temperature
–Reduces mobility
–Reduces V
t
I
ON
decreases with temperature
I
OFF
increases with temperature
V
gs
ds
I
increasing
temperature

28. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 28
So What?
So what if transistors are not ideal?
–They still behave like switches.
But these effects matter for…
–Supply voltage choice
–Logical effort
–Quiescent power consumption
–Pass transistors
–Temperature of operation

29. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 29
Parameter Variation
Transistors have uncertainty in parameters
–Process: L
eff
, V
t
, t
ox
of nMOS and pMOS
–Vary around typical (T) values
Fast (F)
–L
eff: short
–V
t
: low
–t
ox
: thin
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
nMOS
p
M
O
S
fastslow
s
lo
w
f
a
s
t
TT
FF
SS
FS
SF

30. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 30
Environmental Variation
V
DD
and T also vary in time and space
Fast:
–V
DD
: high
–T: low
Corner Voltage Temperature
F 1.98 0 C
T 1.8 70 C
S 1.62 125 C

31. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 31
Process Corners
Process corners describe worst case variations
–If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
–nMOS speed
–pMOS speed
–Voltage
–Temperature

32. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 32
Important Corners
Some critical simulation corners include
Purpose nMOS pMOS V
DD
Temp
Cycle time S S S S
Power F F F F
Subthreshold
leakage
F F F S