Non overlapped melay 1010 sequence detector implemented on xilinx spartan 3e kit

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Software :- Xilinx ISE
Hardware :- Spartan 3E
Device :- XC3S500E
Language :- Verilog

1. Design and Development of ASIC for Non -Overlapped “1010” Sequence Detector RaHUL JETHVA – 12BEC037 Jatin Koshiya – 12BEC040 Guided By :- dR.USHA MEHTA Major Project Review - III

2. OUTLINE Objective Work done till Review – I Work done till Review – II Schematic Implemented in Mentor Graphics Results Conclusion Future Work References

3. OBJECTIVE Objective is to successfully design and development of ASIC for non-overlapping 1010 sequence detector using FPGA prototyping.

4. Work Done Till Review – I

5. Work Done Till Review – II

6. Post Mapping View of Non-Overlap 1010 Sequence D etector Figure 1 Post Mapping View in cyclone II

7. RTL View of Non-Overlap 1010 Sequence Detector Figure 2:- RTL View

8. RTL View of Non-Overlap 1010 Sequence Detector Figure 3:- RTL View

9. Hardware Utilization Cyclone II Xilinx Spartan 3E D Flip-Flop 3 2 3 Input AND gate 3 3 2 Input AND gate 7 3 Input OR gate 1 2 Input OR gate 1 2 NOT gate 6 10 Table :- 1 Hardware Utilization

10. Schematic of D Flip-Flop in Mentor Graphics Figure 4 :- Schematic of D flip-flop

11. Output of D Flip-Flop Figure 5 :- Output diagram of D flip flop

12. Schematic of 1010 Sequence Detector Figure 6 :- Schematic of 1010 sequence detector prepared from Spartan 3E RTL view

13. Output Figure 7 :- Output of Sequence detector

14. Schematic of 1010 Sequence Detector Figure 8 :- Schematic prepared from the post mapping of Cyclone II

15. Final Output of Non-Overlapped 1010 S equence D etector Figure 9 :- Final Output 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1

16. Output – When repeated sequence Figure 10 :- Output diagram of 1010 non-overlapped sequence 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1

17. Output when repeated 1’s and 0’s Figure 11 :- Output diagram when inputs given are 1’s and 0’s.

18. Conclusion After implementing non-overlap 1010 mealy and moore FSM on Cyclone II and Xilinx Spartan – 3E we conclude that the hardware used in mealy FSM is less as compared to moore FSM. On designing Non-Overlap 1010 Mealy sequence detector in Mentor Graphics software, we Successfully can detect the Non-Overlap 1010 Sequence.

19. Future Work

20. REFERENCES Samir Palnitkar, Verilog vhdl – A Guide to digital design and synthesis , Altera Corporation (2011), “ Altera Tutorial – Verilog HDL basic ”. Chris Fetchler (2008), “ Finite State Machines in Verilog ” , Department of Electrical Engineering and Computer Science, Berkley. Xilinx Spartan 3E FPGA Family Data Sheet , Retrieved from http :// www.xilinx.com/support/documentation/data_sheets/ds312.pdf Xilinx Spartan 3E User Guide , Retrieved from http:// www.xilinx.com/support/documentation/user_guides/ug331.pdf Introduction to FSM , Retrieved from http://www.asic-world.com