NU clock skew and timing of pipeline .pdf

1. Clock Skew
Presented by: Ahmed Abdul-Salam

2. Types of wires
•Signal wires
-Random
•Power wires
-DC
-Feeds all cells in chip
•Clock wires
-pure AC change each cycle
-feed all regs
CLK

3. Clock
•Large #regs reflect large capacitance
•Large buffer (inverter chain)
•Absolute delay is not the problem
•Wire is not a lambed-C
Buffer
R1 R2 R3
Logic1 Logic2
CLK
Large-C
DelayDelay

4. Impact of RC-wire on Clk in pipeline
CLK_R1
CLK_R2
CLK_R3

5. Pipelining
•Data should be stabilize at reg2 input
next edge of reg2_CLK

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CLK
Buffer
R1 R2
Logic1
CLK
t
cqt
pdt
su
1
st
edge of
R1 clk
2
nd
edge of
R2 clk

6. Pipeline (with skew +ve)
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•That may solve setup time violations
Is skew always good..??
Buffer
R1 R2
Logic1
CLK
Delay
CLK_R1
CLK_R2
T ??????

7. Pipeline (with skew -ve)
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Buffer
R1 R2
Logic1
CLK
Delay
CLK_R1
CLK_R2
T
??????
•The previous ex assume data and clock
propagating in same direction

what if data flows from reg2 to reg1 ?

8. Types of skew
Positive skew (R1-> R2) Negative skew (R2-> R1)
CLK
Data
CLK
Data
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9. Hold time
•Data should be steady at reg2
input for time t
hold before new
data arrives
•t
pd and t
cd
•Hold time condition (no skew)
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ℎ????????????�≤??????
�??????+??????
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CLK
Buffer
R1 R2
Logic1
CLK
t
cq
t
cd
t
hold
t
cd
: fastest path at logic 1
t
pd
: slowest path at logic1
New data
arrival point

10. Hold time (skew)
Buffer
R1 R2
Logic1
CLK
Delay
CLK_R1
CLK_R2
t
cq
??????
t
cd
t
hold
Positive skew :
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ℎ????????????�≤??????
�??????+??????
��−??????
Negative skew :
??????
ℎ????????????�≤??????
�??????+??????
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