plds - Programable logic devices VLSI.pdf

PLDS- Programable logic devices VLSI
XC9500 CPLD Architecture

2. Programmable Logic Devices
¾
They are available in standard configurations from
a catalogue of parts and are sold in very high volumes. ¾
They may be configured or programmed to create a
part customized to a specific application. ¾
No customized mask layers or logic cells are used.
¾
Fast design turnaround.
¾
Single large block of programmable inter-connect.
¾
A matrix of logic Marco-cells that
usually consists
of programmable array logic followed by FF or latch is used.

3. Types of PLD’s
¾
ROM.
¾
PAL.
¾
PLA.
¾
SPLD.
¾
CPLD.

4. ROM

5. Types of ROM
1.Mask-Programmable ROM
-Permanent data storage -economically feasible for large production
2.Erasable Programmable ROM
-Special Charge Storage mechanism -A PROM Programmer used to provide
voltage pulses.
-can be reprogrammed limited no.of times
3.EEPROM
-
c
an be reprogrammed limited no.of times
4.Flash ROM
-
B
uilt-in Programming and erase Facility

6. PLA
Both AND & OR-array are programmable

7. Example of PLA
Realize the Following function using PLA :
F0 = sop m(0, 1, 4, 6) = A’B’ + AC’ F1 = sop m(2, 3, 4, 6, 7) = B + AC’ F2 = sop m(0, 1, 2, 6) = A’B’ + BC’ F3 = sop m(2, 3, 5, 6, 7) = AC + B

8. PLA with 3 input, 5 Product Terms, and 4 Outputs

9. nMOS
NOR Gate
Conversion for NOR-NOR to AND-OR

10. AND-OR Array Equivalent
PLA Table

11. Realize following function using a PLA :
F1=sop m(2,3,5,7,8,9,10,11,13,15) F2=sop m(2,3,5,6,710,11,14,15) F3=sop m(6,7,8,9,13,14,15)

12. Minimized functions
F1= bd + b’c + ab’ F2= c + a’bd F3= bc + ab’c’ + abd

13. Multiple output K-maps
Reduced PLA Table

16. Programmable Array Logic
(PALS)
-AND-array programmable while OR-array Fixed
Combinational PAL Segment
-
F
usible links are
selectively blown

17. Segment of a Sequential PAL

18. PLDs
like 22CEV10 are capable of implementing a
sequential N/W but not a complete system design. Programmable Gate Arrays and Complex
Programmable
Logic Devices are capable of implementing a complet
e

system design on a single chip.

19. XC9500 CPLD Family
Features: High performance:
-
5
ns pin-to-pin logic delays on all pins
Large density range:
-36 to 288 macrocells with 800 to 6400 usable
gates
5V In-system programmable:
-Endurance of 10,000 program/erase cycles -Program/Erase over full commercial voltage
and temp.range
supports parallel programming of multiple XC9500 devices
-24mA high drive outputs

20. ARCHITECTURE DESCRIPTION
-
m
ultiple FBs and IOBs fully interconnected by Fast
CONNECT switch matrix.
-
I
OB provides buffering for device inputs and outputs.
-
E
ach FB has programmable logic capability with 36
inputs and 18 outputs.
-
F
SM connects all FB o/ps and I/p signal to FB I/ps.
-
F
or each FB, 12-18 o/ps and associated o/p enable
signals drive to the IOBs.

21. XC9500 CPLD ARCHITECTURE

22. XC9500 FUNCTION BLOCKS

23. XC9500 MACROCELL

24. MACROCELL CLOCK & SET- RESET CAPABILITY

25. PRODUCT TERM ALLOCATOR

26. PRODUCT TERM ALLOCATION
WITH 15 PRODUCT TERMS

27. PRODUCT TERM ALLOCATOR LOGIC

28. FASTCONNECT SWITCH MATRIX

29. I/O BLOCK AND OUTPUT ENABLE CAPABILITY

30. EPLD FAMILY
„
Logic density of 300-900 gates
„
Device erasure and reprogramming with nonvolatile EPROM configuration element
„
Logic delay up to 10ns
„
Low power consumption
„
Can be erased with ultraviolet light
allowing design
changes to be implemented quickly.

31. GENERAL DESCRIPTION
„
Uses sum-of-product logic and a programmable register.
„
Sum-of-product: programmable -AND/fixed-OR structure ; implement logic up to eight product terms.
„
Programmable register: can be programmed for D,T,SR or JK F/F or can be bypassed for combinational operation.
„
Macrocell register: can be clocked either by global clock or by any input or feedback path to the AND array.

32. FUNCTIONAL DESCRIPTION
Classic architecture includes following elements:
„
Macrocells
„
Programmable registers
„
Output enable/clock select
„
Feedback select

33. MACROCELL
„
Can be configured for combinational or sequential logic operation.
„
Eight product terms form a prog.AND-array.
„
Additional product term
for
asynchronous clear
control
of the internal register.
„
Another product
term
generates output enable or a logic array
generate
d

clock.
„
Eight product terms
feed
the 8-I/p OR-array.

34. OUTPUT ENABLE/ CLOCK SELECT

35. -
T
wo operating modes mode0 and mode1
-
C
ontrolled by a single programmable bit.
-
C
an be individually configured for each
macrocell.
Mode 0
:
-
t
ri-state output buffer controlled by single product term.
-
O
E=’1’
=> output buffer enabled.
-
O
E=’0’
=> output has high impedance value
-
m
acrocell
f
lip-flop clocked by global clock input signal.
Mode 1
:
-
O
E buffer is always enabled.
-
m
acrocell
r
egister can be triggered by an array-clock
signal generated by a product ter
m
.

36. FEEDBACK SELECT
-
C
ontrolled by feedback
multiplexor.
-
A
llows the designer to feed either the
m
acrocell
o
utput
or the I/O pin input associated with the
m
acrocell
b
ack
into the AND-array.
-
m
acrocell
o
utput can be either the q-output of the
programmable register or the combinatorial output of the macrocell.

37. PEEL-
P
ROGRAMMABLE ELECTRICALLY
ERASABLE LOGIC ARRAY
ƒ
large
P
LAs
t
hat include
logic
m
acrocells
with
flop-flops and feedback to the logic planes.
ƒ
A programmable AND- plane that feeds a programmable OR- plane.
ƒ
Outputs of OR-plane divided into groups of 4 600 to 2800 equivalent gates logic capacity.

38. LOGIC CELL IN PEEL ARRAY
„
Includes: -
a
flip-flop
configurable as D, T or JK
-
t
wo
multiplexors
.

39. PEEL Family
-
provided by Integrated Circuit Technology.
-
Useful for lower pin-count applications.
-
Offering 20-44 pins
-
Speeds as fast as 5ns
-
Additional architectural features(more inputs, product terms, macrocell functions)allow more logic to be put in every part.
-
PEEL arrays are CPLDs with advanced architectural features packed into 24,28 and 44-pin packages.

40. XILINX 3000 SERIES FPGAs
-
C
onsists array of 64 CLBs surrounded by a ring of 64 IOBs
-
I
nterconnections between blocks are programmed by
storing data in internal
Configuration memory cells

41. LAYOUT OF A ROGRAMMABLE LOGIC CELL ARRAY
(some part of it)

42. CONFIGURATION MEMORY CELL

43. XILINX 3000 SERIES LOGIC CEL
L

44. COMBINATORIAL LOGIC OPTIONS

45. XILINX 3000 SERIES I/O BLOCK

46. Direct interconnection between adjacent blocks
General-purpose interconnects

47. VERTICAL AND HORIZONTAL LONG LINES

48. XILINX XC4000 SERIES CLB

49. XILINX XC4000 WIRE SEGMENTS

50. ARCHITECTURE OF ALTERA FLEX
8000 FPGA

51. ALTERA FLEX 8000 LOGIC
ELEMENT

52. ALTERA FLEX 8000 LOGIC
ARRAY BLOCK

53. ARCHITECTURE OF
FLEX
10K FPGA

54. ALTERA APEX 20K
„
256–3,456
LABs, each of which contains 10 Logic
Elements (LEs), so a chip
contains 2,560–51,840 Les,
162,000–2,391,552 usable gates
„
16–216 Embedded System Blocks (EABs), each of which can provide 32,768–442,368 bits of memory
„
Can implement CAM, RAM, dual-port RAM, ROM, and FIFO.

55. APEX LABS AND INTERCONNEC
T
Logic Array Blocks -
10 Les
-
e
ach LE connects to 2 local interconnect,each local
interconnect connects to 10
LEs.
-
E
ach LE can connect to 29 other
L
Es through local
interconnect.
Logic element -
4
-input LUT,carry chain, cascade chain, same as FLEX devices
Interconnect -
M
egaLAB
interconnect between 16
LABs, etc. inside each
MegaLAB
-
F
astTrack
row and column interconnect between MegaLABs0

56. APEX EMBEDDED SYSTEM BLOCKS
-
E
ach ESB can act as a
m
acrocell
and provide product terms
-
E
ach ESB gets 32 inputs fr
om
local interconnect, from
adjacent LAB or MegaLAB
interconnect
-
I
n
this mode, each ESB contains 16 macrocells, and each
macrocell
c
ontains 2 product terms and a programmable
register (parallel expanders also provided)
-
E
ach ESB can also act as a me
mory block (dual-port RAM,
ROM, FIFO, or CAM memory) configured in various sizes