Consider Buck Converter control loop with voltage
mode control
Introduction to Control Issues
+
-
Gv(s)
V
REF
Voltage
controller
+
+
K
v
S
Gconv(s)
v
o
SO
O
SO
CONV
V
D
K
RsLLCs
V
sG
1/
)(
2
Converter
We want V
O
to be the same as V
REF
at DC (ie zero steady
state error
Make G
V
(s) have a huge gain (theoretically infinite) at DC by
including an integrator in G
V
(s)
Then V
O(=0) = V
REF(=0)
The perturbation v
S
(s) is a “distrubance” to the control loop
normally caused by the fact the V
S
is provided by a rectifier
and has ripple at 100Hz (120Hz in the US)
Need to “reject” this in the output voltage V
O
Introduction to Control Issues
)()(1
)()(
)(
)(
sGsG
sGsG
sV
sv
CONVV
CONVV
REF
O
)()(1
)(
)(
)(
sGsG
sKG
sv
sv
CONVV
CONV
S
O
Need to have G
V
as large as possible at 100Hz to minimise
“feedthrough” of the 100Hz disturbance
Also need to make sure that G
V
is small at the switching
frequency to avoid possible instability (all our averaging
approach to modelling/control is invalid if the loop gain at
the switching frequency is not v-small)
We will look briefly at design using the BODE approach –
since this seems the most popular approach for DC-DC
converters in:
Textbooks, research papers, industry application notes etc
Bode design is based on the concepts of “Gain Margin” and
“Phase Margin”
We know that a feedback system is just unstable if the loop
gain is unity at a frequency where the loop phase shift is
180
O
(assuming a negative feedback loop which adds
another 180
O
when the error is calculated)
Hence define
GAIN MARGIN = difference between loop gain and unity
(normally expressed in dB) at the frequency where the
phase shift is 180
O
PHASE MARGIN = (180 - Loop Phase Shift) at the
frequency where the loop gain is unity
For most simple systems it is sufficient to design to ensure
adequate phase margin to get a stable system with a
satisfactory response
Introduction to Control Design (1)
(Bode approach)
Gain and phase margin definitions
Introduction to Control Design (2)
(Bode approach)
This diagram applies to loop gain and includes the
effect of a minus sign in the error calculation (ie
negative feedback loop)
At low frequencies we assume G1(s)G2(s) is large
and C(s) follows R(s)
As frequency increases G1(s)G2(s) becomes smaller
The frequency where G1(jw)G2(jw)=1 is called the
“Crossover Frequency”
It defines the frequency where C(s)/R(s) is approx
3dB lower than its low frequency value – ie the
system “Bandwidth”
Introduction to Control Design (3)
(Bode approach)
Importance of “Crossover frequency”
Consider simple control loop
+
-
G1(s)
R(s)
Controller
G2(s)
Plant
C(s)
)(2)(11
)(2)(1
)(
)(
sGsG
sGsG
sR
sC
The general procedure for Bode design is
Determine the Plant transfer function
Assuming we are doing voltage mode control, this
is v
O
(s)/d(s)
Calculate the frequency response characteristics
(s=j)
Choose the Crossover Frequency
This is desired to be a high as possible – but needs
to be a sensible choice (experience)
Choose the target Phase Margin
Phase Margin determines the damping of the closed
loop response
Normally go for about 60
O
to get reasonable
damping (less phase margin = less damping)
Choose a target controller TF and calculate design
Iterate if chosen values don’t work (experience)
The method of H Dean Venable is widely quoted in
DC-DC converter design (see Handout)
Introduction to Control Design (4)
(Bode approach)
Example design (done in Lecture)
Design a buck converter with the following steady
state parameters/conditions
V
S=50V, V
O=20V, f
SW= 50kHz
I
O = 10A (rated), I
L=4A, V
O=1%
Design a voltage mode closed loop controller
using the approach of Venable
Introduction to Control Design (5)
(Bode approach)
Comments on example design
The example design works and
Is stable!
Gives zero steady state error
Gives some rejection of 100Hz ripple
However
The transient response is not very good with too
much “ringing”
This will get worse if we reduce the load on the
converter (less damping of resonant pole in TF)
Probably the design could be improved with this
controller (but not much) or a more sophisticated
controller could be tried
However we can see from this example that the
resonant pole in the TF will always cause problems for
voltage mode control
This was one of the main motivations behind the
development of current mode control (see later)
Introduction to Control Design (6)
(Bode approach)
We have seen that it is difficult to get good closed loop
control of the Buck circuit using voltage mode control
The situation is much worse with the Boost and Flyback
circuits
The TF dynamics change (considerably) with changing
operating point
Recall earlier boost converter waveform handout
The TF has a ZERO on the right hand side of the s-plane
The detrimental influence of this can be understood both in
terms of BODE
Increases both GAIN and PHASE LAG as frequency
increases – reduces gain and phase margin
Or in terms of ROOT-LOCUS
In the closed loop root-locus the poles move towards the
open loop zeros
A zero on the right hand side will attract the poles towards
the unstable part of the s-plane
The physical origin of the ZERO is due to the switch between
the L and C
Increasing D has the effect of reducing the time the inductor
current is fed to the output load/capacitor
Initially Vo reduces until I
L has had time to increase
This lag causes the ZERO
Voltage mode control of Boost/Flyback in CCM very difficult
Introduction to Control Design (7)
(Boost and Flyback)
Main imperfections are resistance in L and resistance
in C (effective series resistance – ESR)
ESR has the biggest effect on dynamics
Consider a Buck converter with capacitor ESR
Effect of imperfect components
on converter dynamics (1)
Equations
Effect of imperfect components
on converter dynamics (2)
Mode Matrices for Averaging
Effect of imperfect components
on converter dynamics (3)
Going through the state space averaging and
linearisation procedure as before (need to use the output
equation to get v
O
(s)/d(s) rather than v
C
(s)/d(s)) gives
(try it!):
TF denominator is changed is – but not by much when
you consider typical values
Main difference is the addition of a LEFT HAND ZERO
This ZERO is normally at quite a high frequency
Causes higher gain at the switching frequency than
predicted by earlier model
May cause problems with instability if not included in the
design
Although we have only looked here at the BUCK
converter – the capacitor ESR has the same effect in
the other converters
)/(/)(
)1(
)(
)(
2
CCC
SOC
C
o
RRRRRCRRLsLCs
VCsR
RR
R
sd
sv
Effect of imperfect components
on converter dynamics (4)
Averaged Switch Modelling(1)
Averaged switch modelling is another approach for
obtaining the control behaviour of switching circuits
Philosophy
The top part of the circuit is something we know how to
manipulate and model
Deal with averaging the switch network separately and then
insert it back into the original circuit to get a complete
LINEAR TIME INVARIANT equivalent circuit
Vs Vo
Linear time-
invariant part of the
network (ie L, C etc)
Switch network
CONVERTER CIRCUIT
Averaged Switch Modelling(2)
Buck Converter
R
L
CV
S V
O
V
L
i
O
i
Q
i
D
i
L
i
C
Remove switch circuit
i
2
v
1 v
2
Duty
cycle d
i
1
Averaged Switch Modelling(3)
Buck Converter
I
1
Equivalent averaged switch circuit with controlled sources
DI
2
DV
1
I
2
Assume linear ripple in inductor current and small change in
Vs over each switch cycle
Average input/output quantities for the switch network over
1 cycle
Averaged Switch Modelling(5)
Buck Converter
Ideal transformation element passing all frequencies
Has the voltage, current and impedance transformation
properties of an ideal transformer with N1/N2 = 1/D
O
but
unlike a normal transformer:
It works also at DC
No isolation is implied
Note that this circuit element is a mathematical artifice – no
such single circuit element exists in reality
1 : D
O
Averaged Switch Modelling(6)
Buck Converter
Insert averaged switch model into the rest of the converter
R
L
C
1 : D
O
e f h
g
e = V
S0
+ v
S
f = dI
L0
g = dV
S0
h = V
0
+ v
O
This circuit models both small signal behaviour and steady
state behaviour
Normal circuit techniques can be used to calculate
Transfer functions
Output impedance
Input impedance
etc
Averaged Switch Modelling(7)
Boost Converter
Remove switch circuit
R
D
L
CV
S V
O
i
O
i
Q
i
Di
L
i
C
Q
i
2
v
1
v
2
i
1
Averaged Switch Modelling(8)
Boost Converter
I
2
Equivalent averaged switch circuit with controlled sources
(1-D)V
2
I
1
Proceed as before
(1-D)I
1
v
1 v
2
Averaged Switch Modelling(9)
Boost Converter
Equivalent linearised switch circuit
Perturb as before (do it!) to get
(1-D
O
) : 1
dV
2O dI
1O
Averaged Switch
Modelling(10)
Boost Converter
Insert averaged switch model into the rest of the converter
R
L
C
(1-D
O):1
e f h
g
e = V
S0
+ v
S
f = dI
L0
g = dV
0
h = V
0
+ v
O
How can we get v
O
(s)/d(s) from this?
Need to manipulate the circuit
Averaged Switch
Modelling(11)
Boost Converter
Circuit manipulation
R
L
C
(1-D
O
):1
e f h
g
e = V
S0
+ v
S
f = dI
L0
g = dV
0
h = V
0
+ v
O
Move f to the other side of the transformer and scale
accordingly
R
L
C
(1-D
O):1
e h
g
f
f = dI
L0/(1-D
O)
Averaged Switch
Modelling(12)
Boost Converter
Move f to the other side of L and add a voltage source to
model the voltage drop across L due to f
Move L to the other side of the transformer and scale
accordingly
R
L
C
(1-D
O):1
e h
g
f
m = sLdI
L0
/(1-D
O
)
m
R
L/(1-D
O)
2
C
(1-D
O
):1
e h
g
f
e = V
S0
+ v
S
f = dI
L0
/(1-D
O
) g = dV
0
h = V
0
+ v
O
m = sLdI
L0
/(1-D
O
)
m
Circuit analysis gives
use the steady state relationships:
1
)1()1(
)1(
1
)1(
)(
)(
22
2
22
OO
OO
SO
o
DR
sL
D
LCs
RD
sL
D
V
sd
sv
RD
V
Iand
D
VV
O
SO
LO
O
SOO 2
)1()1(
1
Giving (as before):
Averaged Switch
Modelling(13)
Boost Converter
1
)1()1(
)1(
1
)1(
)(
)(
22
2
2
OO
O
LO
O
O
o
DR
sL
D
LCs
D
sLI
D
V
sd
sv
Averaged Switch
Modelling(14)
Boost Converter
The equivalent circuit produced by “switch averaging” is a
very convenient way of visulising what is happening in the
converter with respect to low frequency dynamics
We can see clearly that the simple LC filtering effect in the
Buck converter is replaced by something more complex in
the Boost converter
The effective inductance is the actual inductance scaled by
(1-D
O)
2
and clearly changes with duty cycle
This explains why the dynamics of the circuit change with
operating point
The equivalent circuit can be used to predict any low
frequency behaviour we want
All converters can be expressed in this basic form leading to
the so called “Canonical Equivalent Circuit”
Used to study generic behaviour of converters without
having to analyse each specific type
Canonical Form
R
L
eff
C
1:M(D)
e h
g
f
e = V
S0 + v
S h = V
0 + v
O
M(D) L
eff
g f
BUCK
BOOST 1/(1-D
O
) L/(1-D
O
)
2
dI
L0
/(1-D
O
)sLdI
L0
/(1-D
O
)+ dV
0
FLYBACK D/(1-D
O
) L/(1-D
O
)
2
V
0
/R(1-D
O
)
2
(V
0
/D
2
)(1-sDL/(R(1-D
O
)
2
)