ppt.ppt on didgital logic design by muskan.s

on vlsi

1. Digital logic design
By
Muskan. S
(Embedded System and VLSI)

2. CONTENTS
Pseudo-NMOS
Dynamic Combinational Logic
Domino Logic
Pass Transistor Logic
Complementary Pass Transistor Logic
Complex CMOS Gates

3. Ratioed-logic
Load is PMOS with gate tied to ground
VOHisVDD.VOLisnotground.
VOL=(Rpdn/Rload+Rpdn)*VDD
At VOL PMOS is in saturation and NMOS is in triode.
For a faster low to high transition the current should be high and hence
bigger 6p required.
Pseudo-NMOS

4. Pseudo-NMOS
(8)(to)
Some commonly used ways for pseudo-NMOS inverters

5. Problems and Advantages of Pseudo-
NMOS
Problems :
Voltage transfer characteristic is asymmetrical Rise
and fall time are asymmetrical
Static power consumption
Advantages:
High speed
Useful when designing complex gates with large
fan-in.

6. Dynamic Combinational Logic
■Avoidsstaticpowerdissipation
■Uses a sequence of pre-charge and Evaluate to realize complex
logic functions.
■The inputs to the logic are not allowed to change and are zero in
pre-charge phase.
■If the output is discharged it can not be charged again.

7. Advantages of Dynamic Combinational logic
over static combinational logic
NumberoftransistorsarelessN+2comparedto
2N.
Non-Ratioed.
Nostaticpowerconsumption
Highswitchingspeed.

8. Problems Associated with
dynamic logic
Chargeleakage
Chargesharing
Clockfeedthrough

10. Cascading Dynamic gates
■Problem arises when Dynamic
gates are cascaded.
ThePDNofsecondstageisina
conductingstage.Thisleadstofaulty
operationofthegates.
Correct operation is guaranteed as
long as the inputs make a single 0-1
transition.

11. Dynamic sequential Circuits
■CMOS based circuit is race free as
long as all the logic functions
implemented between latches are
noninverting.
■During overlap only pull-up or
pull-down is activated.
■Figure shows a 1-1 overlap. The
only way race can happen is if the
function is inverting.

12. Domino Logic

13. Why Domino?

14. Properties of Domino Logic
□Only non-inverting logic can be implemented, fixes
include
canreorganizethelogicusingBooleantransformations
usedifferentiallogic(dualrail)
usenp-CMOS(zipper)
Veryhighspeed
staticinvertercanbeoptimizedtomatchfan-out(separation
offan-inandfan-outcapacitances)

15. Differential (Dual Rail) Domino
Due to its high-performance, differential domino is
very popular and is used in several commercial
microprocessors!

16. Inelectronicspasstransistorlogic(PTL)
describesseverallogicfamiliesusedinthe
designofintegratedcircuits.
Itreducesthecountoftransistorsusedtomake
differentlogicgates,byeliminatingredundant
transistors.
Disadvantagethatoutputlevelsarealways
lowerthantheinputlevel.
Pass Transistor Logic

17. Inconventionallogicfamiliesinputisappliedto
gateterminaloftransistorbutinPTLitisalso
appliedtosource/drainterminal.
ThesecircuitsactasswitchesuseeitherNMOS
transistorsorparallelpairofNMOSandPMOS
transistorcalledTransmissiongate.
HerethewidthofPMOSistakenequaltoNMOSso
thatbothtransistorscanpassthesignal
simultaneouslyinparallel.

18. nMOSpasses
•
•
strong‘0’
Weak‘1
pMOSpasses
•
•
Strong‘1’
Weak‘0’
g
s d
g
s d
g=1input‘0’
OutputStrong‘0’
g=1input‘1’
Outputweak‘1’
g=0input‘0’
Outputweak‘0’
g=0input‘1’
Outputstrong‘1’

19. pAsstrAnsIstorlogIc
◦So when g=1
g
ba
gb
g=0, gb=1
Switch is
open
So when
g=1
g=1, gb=0
Switch is
closed

20. Fewer Devices To Implement The Logical Functions
As Compared To CMOS.
Example AND Gate.
WhenBis“1”,topdevice
turnsonandcopiesthe
inputAtooutputF.
WhenBislow,bottom
deviceturnson
andpassesa“0”.

21. Some logicalcircuitsusingPTL

22. PTL has been successfully used to implement digital
systems which are smaller, faster, and more energy
efficient than static CMOS implementations for the
same designs.

23. PassTransistorLogicOctober9,2012 17

24. Levels of Abstraction -MOS switch and Inverter-
Out=NOT(In)
Out=~(In)
Equation
In Out
0 1
1 0
X X
Truth Table
LOGICAL
PHYSICAL
Complex CMOS Gates

25. Important rules
•NFET’spulldown,PFET’spullup
•PullupandpulldownNOTatthesametime
•OutputalwaysconnectedtoVDDorGND

26. NAND Gate

27. NOR Gate

28. Multiplexer

29. Gate Construction
•Truthtablemethod
•Complementarystructures

30. Truth table method
• Example

31. Complementary structures
•BuildthePUPfromthePDNorviceversa
•Replace
—PMOSwithNMOS(andviceversa)
— Parallelbrancheswithseriesbranches(andvice
versa)
•Signalsgoingtoinputs:unchanged

32. Complementary structures
• Example

33. Complementary structures
• Example
X x
(c)

34. D
D = (X + Y) • Z

35. Boolean equation method (I)
• Reduction
• Expansion

36. Boolean equation method (II)
• Example