Presentation 8 (6).pptx................................

1. Major project presentation on "LOW POWER FLIP-FLOP DESIGN USING GDI TECHNIQUE IN 120nm"   Under the guidance  of Mrs.P.S SUREKHA(Associate professor & HOD) ​ ​                                         Presented by :​                                                         J.Shireesha-18UJ1A0430​                                                      J.Pranitha-18UJ1A0431​                                                         K.Sowjanya-18UJ1A0435​                                                                     K.Venkat   sai  kumar-18UJ1A0436 ​

2.                                      ABSTRACT It  introduces a high speed, low power, synchronously clocked NAND/NOR gate based JK flip-flop by using modified Gate Diffusion Input (GDI) procedure in 120 nm technology. Here we are using two types of JK flip-flops which are NAND gate based and NOR gate based. In this project, we need to address issues such as  High power consumption and reduction of utilization of number of transistors .  Enhancing  the performance of the JK flip flop by implementing GDI technique.  GDI technique helps in designing low-power digital combinational circuits by which we can eradicate demerits of CMOS  techniques. This technique allows reducing power consumption, propagation delay and area of digital circuits while maintaining low complexity of logic design. 

3.                        EXISTING METHOD The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and  R are  equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of  SR Bistable Latch  except for the addition of a clock input.  JK flip flop 

4.                          PROPOSED METHOD   For reduce the power consumption and number of transistor we are applying GDI methodology .   Morgenshtein  et al. investigated a high-speed and multipurpose logic style for low power electronics design, known as Gate Diffusion Input (GDI), with reduced area and power necessities, and proficient of implementing a broad variety of logic functions. Figure shows basic GDI logic cell, which is used for implementing verity of logic functions and circuits at low power and high speed design where G, P and N are three inputs and output is taken from D terminal. But this basic Gate Diffusion Input logic style suffers from some practical limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections. These limitations can be overcome by modified gate diffusion input logic style.                                                

5.                                  CONCLUSION In the VLSI , main issue is high power consumption and area. So in this,  we will reduce the power consumption and number of transistor for the JK flip flop for both design .  We will propose GDI technique by which the number of transistors and area get reduce.

6.                   THANK YOU