presentation_fabrication_1483089689_242068.pptx

integrated circuit fabrication

1. Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up. Topics

2. IC Fabrication Steps

3. IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO 2 ) is insulator. Fabrication processes

4. Simple cross section substrate n+ n+ p+ substrate metal1 poly SiO 2 metal2 metal3 transistor via

5. Mask patterns are put on wafer using photo-sensitive material: Photolithography

6. First place tubs to provide properly-doped substrate for n-type, p-type transistors: Process steps p-tub p-tub substrate

7. Pattern polysilicon before diffusion regions: Process steps, cont’d. p-tub p-tub poly poly gate oxide

8. Add diffusions, performing self-masking: Process steps, cont’d p-tub p-tub poly poly n+ n+ p+ p+

9. Start adding metal layers: Process steps, cont’d p-tub p-tub poly poly n+ n+ p+ p+ metal 1 metal 1 vias

10. n-type transistor: Transistor structure

11. 0.25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

12. n-type (tubs may vary): Transistor layout w L

13. Drain current characteristics

14. Linear region (V ds < V gs - V t ): I d = k’ (W/L)(V gs - V t )(V ds - 0.5 V ds 2 ) Saturation region (V ds >= V gs - V t ): I d = 0.5k’ (W/L)(V gs - V t ) 2 Drain current

15. Typical values: n-type: k n ’ = 170  A/V 2 V tn = 0.5 V p-type: k p ’ = 30  A/V 2 V tp = -0.5 V 180 nm transconductances

16. Use 180 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. V gs = 0.7V: I d = 0.5k’(W/L)(V gs -V t ) 2 = 5.3  A V gs = 1.2V: I d = 62  A Current through a transistor

17. Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance. Basic transistor parasitics

18. Gate capacitance C g . Determined by active area. Source/drain overlap capacitances C gs , C gd . Determined by source/gate and drain/gate overlaps. Independent of transistor L. C gs = C ol W Gate/bulk overlap capacitance. Basic transistor parasitics, cont’d

19. CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures. Latch-up

20. Parasitic SCR circuit I-V behavior

21. Parasitic SCR structure

22. Use tub ties to connect tub to power rail. Use enough to create low-voltage connection. Solution to latch-up

23. Tub tie layout metal (V DD ) p-tub p+