Readonly memories DMAcontrollerand .pptx

Carl Hamacher ppt

1. CMOS MEMORY CELL Transistors (T3,T5) and (T4,T6) form the inverters in the latch. For example ,in state 1,the voltage at point X is maintained high by having transistors T3 and T6 on. while T4 and T5 off. If T1 and T2 are turned on bit lines b and b’ will have high and low signals respectively. The power supply voltage is 5V in older CMOS SRAMS 0r 3.3 V in new low voltage versions. Continuous power is needed for the cell to retain its state. If the power is interrupted the cells contents will be lost. Advantages: Very low power consumption.

2. Fast Page Mode Suppose if we want to access the consecutive bytes in the selected row. This can be done without having to reselect the row. Add a latch at the output of the sense circuits in each row. All the latches are loaded when the row is selected. Different column addresses can be applied to select and place different bytes on the data lines. Consecutive sequence of column addresses can be applied under the control signal CAS, without reselecting the row. Allows a block of data to be transferred at a much faster rate than random accesses. A small collection/group of bytes is usually referred to as a block. This transfer capability is referred to as the fast page mode feature.

3. SYNCHRONOUS DRAMS Operation is directly synchronized with processor clock signal. The outputs of the sense circuits are connected to a latch. During a Read operation, the contents of the cells in a row are loaded onto the latches. During a refresh operation, the contents of the cells are refreshed without changing the contents of the latches. Data held in the latches correspond to the selected columns are transferred to the output. For a burst mode of operation, successive columns are selected using column address counter and clock.CAS signal need not be generated externally. A new data is placed during raising edge of the clock

4. The row address is latched under the control of RAS signal. The memory takes 2 or 3 clock cycles to activate the selected row. The column address is latched under control of CAS signal. After the delay of one clock cycle the first set of data bits are placed on the data lines. The SDRAM automatically increments the column address to access the next three sets of bits in the selected row,which are placed on the data lines in the next three clock cycles. SD RAMS have built in refresh circuitry.

5. Latency and Bandwidth Latency: It is used to refer to the amount of time it takes to transfer a word of data to or from memory . In case of reading or writing a single word of data,the latency will provides the complete indication of memory performance. In block transfers the term latency is used to denote the time it takes to transfer the first word of data. Bandwidth: The number of bits or bytes that can be transferred in one second.This is referred to as memory bandwidth.

6. Double Data rate SDRAM The standard SDRAM performs all actions on the rising edge of the clock signal. A similar memory device is available which access the cell array in the same way,but transfers the data on both edges of the clock . Since they transfer the data on both the edges of the clock,their bandwidth is essentially doubles for long burst transfers . Such devices are known as double data rate SDRAMS(DDR SDRAMS).

7. Structure of large memories Static Memory systems

8. Dynamic memory systems Large dynamic memory systems can be implemented using DRAM chips in a similar way to static memory systems. Placing large memory systems directly on the motherboard will occupy a large amount of space. Also, this arrangement is inflexible since the memory system cannot be expanded easily. Packaging considerations have led to the development of larger memory units known as SIMMs (Single In-line Memory Modules) and DIMMs (Dual In-line Memory Modules). Memory modules are an assembly of memory chips on a small board that plugs vertically onto a single socket on the motherboard. Occupy less space on the motherboard. Allows for easy expansion by replacement .

9. Memory systems considerations The choice of RAM chips for a given application depends on several factors. Cost Speed Power dissipation Size of the chip.

10. Memory Controller

11. Read-Only Memories (ROMs)