Ripple counter

Ripple Counter

1. Ripple Counter

2. Modulus (MOD) of a counter
•Is the number of differentstates the counter must go
through to complete its counting cycle.
•Is also the counter’s frequency division ratio
•Maximum MOD number = 2
n
, n = number of flip flops.
MOD States
4 00, 01, 10,11
8 000, 001, 010, 011, 100, 101, 110, 111
MOD-8
Counter
16 kHz 2kHz
Number of Flip FlopsMaximumPossible
MOD
2 2
2
= 4
3 2
3
= 8
4 2
4
= 16

3. State Transition Diagram
•Graphical representation of the sequence of states
MOD-4 Counter MOD-6 Counter
MOD-8 Counter
•Each circle represents one possible state, as indicated by the binary number inside the circle
•For example, the circle 001 state (i.eQ
2= 0 , Q
1= 0, Q
0= 1 )
•Each arrow represents the occurrence of a clock pulse and show how one state changes to
another
Q
0
Q
1
Q
2 (LSB)
(MSB)
MOD-16 Counter

4. 4-Bit Ripple UPCounter
CLK
J
K
A
A
CLK
J
K
B
B
CLK
J
K
C
C
CLK
J
K
D
D
* All Jand K
inputs assumed
to be 1.
B
A
Clock
DCBA
(count)
1234 5678 91011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011 1101 1111 0001
1100 1110 0000
12 151314 161718
C
D
Recycle to 0000
(LSB)
(MSB)
LSB –Least Significant BitMSB –Most Significant Bit

5. 3-Bit Ripple DOWNCounter
CLK
J
K
A
A
CLK
J
K
B
B
CLK
J
K
C
C
* All J and K
inputs assumed
to be 1.
1 2 3 4 56 7 8 9
Clock
pulses
Count
(CBA)
B
000 001010011100101110111 000111
Recycles
A(LSB)
C(MSB)
A
B
Observe that for the Down
counter, the clock is
connected to the output.

6. Truncated Counters with MOD Number <2
N
•Example:
A MOD-6 Counter
achieved by clearing the
MOD-8 counter when
Band C= ‘1’
CLK
J
K
A
A
CLK
J
K
B
B
CLK
J
K
C
C
* All Jand K
inputs are 1.
CLR CLR CLR
B
C
C
B
A
Clock
pulses
NAND
output
1234 5678 9101112
CBA
000
100
010
110
111
001
011101
*
*
000001010011100101000001010011100101
(CBA)
Spike/glitch due to B
and C having to go
HIGH first before the
flip flops are reset.

7. Integrated Circuit Ripple Counters
•74LS90 –Single Decade Ripple counter
•74LS92 –Single Divide by Twelve Ripple counter
•74LS93 –Single 4 bit Ripple Counter
•74HC390 –Dual Decade Ripple Counters

8. Internal Logic Diagram for 74LS93
CLK
J
K
Q
Q
CLK
J
K
Q
Q
CLK
J
K
Q
Q
CLK
J
K
Q
Q
CP
0
CP
1
MR
1
MR
2
Q
3Q
2Q
1Q
0
CLR CLR CLR CLR
•Note that for 4 Bit Ripple Counter –the output Q
0must be externally
connected to input CP
1and the clock pulse are applied at CP
0.
•All outputs will be reset to LOW when MR
1and MR
2is high

9. 74LS93 Wired as a MOD-16counter74LS93
MR1 and MR2
are both tied to
LOW
Output Frequency of Q3=
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10. 74HC390

11. 74HC390 as a MOD 10 Counter
10019
10008
01117
01106
01015
01004
00113
00102
00011
00000
Q
3Q
2Q
1Q
0Decimal
Counting Sequence

12. 74HC390 as a MOD 6 Counter
01015
01004
00113
00102
00011
00000
Q
3Q
2Q
1Q
0Decimal
Counting Sequence

14. Preparations for Mini Project