Secrets of the DCM Part 2_________.pptx

Secrets of the DCM

1. Secrets of the DCM: Part 2 Steven Knapp General Products Division ([email protected]) (v1.2, 11-OCT-2004) © 2004 by Xilinx, Inc. All rights reserved. NOTICE: This is an early draft of this presentation. Please visit the Xilinx Sales Partner Web (SPW) for the latest version. http://www.partner.xilinx.com/common/spartan3/faeconf.htm

2. Continuing On … This is a continuation of Secrets of the DCM: Part 1 that covered the following topics … Overview of the DCM and its applications Basic Delay Locked-Loop (DLL) operation Clock Wizard Clock Jitter

3. Workshop Objectives By the end of this class, you will … Understand how the DCM can phase shift clocks Understand how to generate other clock frequencies Learn how to build high-speed data interfaces Overcome various DCM limitations Legitimately say “DCMs D on’t C onfuse M e”

4. Lesson Four Phase Shifting

5. DCM DCM Block Diagram Digital Frequency Synthesizer Phase Shifter (PS) Input Stage Output Stage Delay Taps Status Logic Delay-Locked Loop (DLL) PSINCDEC PSEN PSCLK CLKIN CLKFB RST PSDONE STATUS[7:0] LOCKED CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180

6. Phase Shifting The DCM provides various phase shifting options Dedicated phase shift outputs These signals always maintain their relationship Quadrant: CLK0, CLK90, CLK180, CLK270 Half-Period: CLK2X/CLK2X180, CLKFX/CLKFX180 Fixed or Variable phase shifting Adjust the phase relationship of all DCM clock outputs Requires the DCM’s DLL function

7. Quadrant Phase Shifts CLK90 and CLK270 only available in low-frequency mode ° 1T CLK0 ° 90 ¼T CLK90 T 180 ° ½ CLK180 270 ° ¾ T CLK270 360 ° Phase Shift (degrees) Delay (fraction of clock period) Clock Period (T)

8. Half-Period Phase Shift CLK2X/CLK2X180 and CLKFX/CLKFX180 are similar 180 ° ° ½ T 1T CLK0 CLK180 360 ° Phase Shift (degrees) Delay (fraction of clock period) Clock Period (T) Highly useful for high-performance Dual-Data Rate (DDR) applications Guarantees precise half-period timing

9. DDR Example Clock Inversion at I/O Block Introduces Duty-cycle Distortion < 150 MHz ≥ 150 MHz “Local inversion” Precise Timing with Half-Period Phase Shifting “Complementary”

10. Review: The DLL DLL shifts the feedback until the Clock and the Feedback are in phase (0° phase shift) DLL controls the phase relationship, can be other than 0° Phase Detector Delay Line Clock Feedback Clock Feedback Positive Phase Shift Negative Phase Shift

11. Fixed Phase Shifting Fixed phase shift value set during configuration, unchangeable Affects all DCM clock outputs Clock Outputs Fixed Phase Shift + Limit Fixed Phase Shift – Limit The PHASE_SHIFT attribute determines the initial phase shift position. DCM initially asserts LOCKED with this phase shift value. DCM returns to this value upon RESET. CLKIN Phase Shift Type: Value: 23 Enter the Fixed phase shift value 2.695 ns 32.344 Degrees Resulting fixed phase shift in nanoseconds and degrees of phase shift NONE FIXED Choose FIXED Clock Wizard

12. Checking If You’re Awake A DCM has a FIXED phase shift of 10° What is the phase relationship between CLK0 and CLK90? What is the phase relationship between CLKIN and CLK0? What is the phase relationship between CLKIN and CLK90? Always 90° 100° = 90°+ 10° 10° = 0°+ 10°

13. Delay Line and Frequency Delay line has 255 taps, each 30 ps to 60 ps Maximum guaranteed delay line is 10 ns, ~40 ps per tap Clock inputs above 100 MHz can be shifted a full period (360°) Shift resolution defined by individual tap delay Phase Detector Delay Line Clock Feedback Clock LIMIT

14. Shift Limits < 100 MHz Clock inputs < 100 MHz have clock period longer than the guaranteed tap length (> 10 ns) Can only shift the clock a fraction of the clock period (<360°) Phase Detector Delay Line Clock Feedback Clock BEYOND LIMIT

15. Phase-Shift Limits T CLKIN > FINE_SHIFT_RANGE (Frequency < 100 MHz) T CLKIN = Period of CLKIN input clock T CLKIN ≤ FINE_SHIFT_RANGE (Frequency > 100 MHz) FINE_SHIFT_RANGE = Guaranteed length of delay line = 10 ns (per data sheet)

16. Variable Phase Shifting Clock Outputs The PHASE_SHIFT attribute determines the initial phase shift position. DCM initially asserts LOCKED with this phase shift value. DCM returns to this value upon RESET. CLKIN Fixed Phase Shift + Limit Increment Phase Shift Value Decrement Phase Shift Value Dynamic Phase Shift - Limit Dynamic Phase Shift + Limit After the DCM asserts LOCKED, the FPGA application can increment or decrement the present phase shift value using the Dynamic Phase Shift Control logic. PSEN PSINCDEC PSCLK PSDONE STATUS[0] Enable Increment/Decrement Phase Shift Clock Phase Shift Done Variable Phase Shift Overflow DCM Variable Phase Shift Control Fixed Phase Shift + Limit

17. Variable Phase Shift Timing LOCKED remains asserted during a variable phase shift operation

18. Phase Shift Mathematics Convert Negative Phase Shift to Positive Phase Shift Convert Phase Shift in Degrees to Phase Shift in Nanoseconds Alternate Phase Shift Solutions

19. Lesson Five Clock Synthesis

20. Frequency Synthesis FPGA DCM F n -bits wide F n F High-speed serial data down-converted to slower parallel data Clock Division DCM F F Ÿ m m -bits wide F Slower parallel data up-converted to high- speed serial data Clock Multiplication F Overclocked, time-shared logic DCM F F Ÿ x Clock Synthesis Low cost design technique: Utilize full performance of the FPGA

21. Output clocks are phase aligned when using clock feedback via the CLKFB input. Frequency Synthesis CLKIN CLK0 CLKFB DCM CLK2X CLK2X180 F=2 Ÿ F CLKIN Clock Doubler 50% duty cycle Output available only when DLL_FREQUENCY_MODE=LOW De-skewed Clock F=F CLKIN 50% duty cycle when DUTY_CYCLE_CORRECTION=TRUE CLKDV Clock Divider F= F CLKIN CLKDV_DIVIDE Usually 50% duty cycle, depending on conditions CLKFX CLKFX180 Frequency Synthesizer F= F CLKIN Ÿ CLKFX_MULTIPLY CLKFX_DIVIDE 50% duty cycle Does not require CLKFB input

22. Clock Synthesis Options Function DCM Output(s) Frequency Functional Unit Feedback Required? Clock Doubler CLK2X CLK2X180 2*F CLKIN DLL Yes Clock Divider CLKDV F CLKIN /DIV DLL Yes Frequency Synthesizer CLKFX CLKFX180 F CLKIN *M/D DFS Optional

23. Clock Divider CLKDV output requires the DLL and consequently the CLKFB feedback For Spartan-3, the CLKDV_DIVIDE attribute can be … 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, 16 Lower output jitter when CLKDV_DIVIDE is an integer 50% duty-cycle output usually Except when operating in High Frequency mode and CLKDV_DIVIDE is a non-integer ( i.e., 1.5)

24. Digital Frequency Synthesizer (DFS) CLKFX/180 output frequency controlled by fraction of two attributes CLKFX_MULTIPLY = {2,3,4• • •32} CLKFX_DIVIDE = {1,2,3,4• • •32} Reduce to least common multiple CLKIN and CLKFX/180 outputs are more limited when also using the DLL Using the DLL with the DFS limits the frequency range When used, DDL and DFS are phase aligned every CLKFX_DIVIDE cycles of CLKIN CLKFX_MULTIPLY cycles of CLKFX (from General Setup window)

25. Period Jitter on CLKFX Maximum period jitter for CLKFX output is characterized Depends on multiply and divide values Depends on input and output frequencies Room temperature (25°C) Nominal voltages 50% CLBs and 40 simultaneous outputs switching at 100 MHz Jitter reported by Clock Wizard Spartan-3 jitter is effectively same as Virtex-II Pro http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm

26. Spartan-3 CLKFX Jitter Equations CLKFX/CLKFX180 Output Frequency Peak-to-peak Period Jitter (Unit Interval) Peak-to-peak Period Jitter (ns) B = 0.05 when F CLKIN > 8 MHz, else = 0.04 K = CLKFX_MULTIPLY when CLKFX_MULTIPLY > CLKFX_DIVIDE, else = CLKFX_DIVIDE

27. Jitter on CLKFX (from General Setup window)

28. Cascading DCMs DCMs can be cascaded, but there is no dedicated routing available for this The specified output jitter from the first DCM must not exceed the specified input jitter of the second DCM CLKFX output practically eliminated for the first DCM stage due to jitter Keep second DCM reset until first DCM locks WARNING: CLKDV does not toggle until LOCKED 1 Requires three flip-flops to synchronize reset http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19005 Function also available in the DCM Wizard

29. Clock Wizard Cascade DCMs

30. Lesson Six System vs. Source Synchronous Design

31. System Synchronous Assumes a single, system-wide clock DLL path includes delay to compensate for clock path Ensures no hold time requirement at the receiver System synchronous is the default assumption

32. Source Synchronous Clock generated by same source as data Typically, clock and data have same phase No compensation for clock path delay Receiver hold time is not an issue Clock MUST be phase shifted in the receiver

33. System vs. Source Synchronous Timing DATA_IN SOURCE_SYNCHRONOUS SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS + Fixed or Dynamic Phase Shift Data capture window or data “eye” A little extra delay guarantees no hold time requirement Application phase shifts clock to middle of data eye

34. Deskew Adjustment in Clock Wizard (from General Setup window)

35. Lesson Seven Optional Divide by 2

36. Dividing Input Clock by 2 Optional divide-by-2 function on CLKIN input Dedicated high-speed toggle flip-flop inside the DCM Divide down a high-frequency clock to the range acceptable to the DCM Clean up a non-50% duty-cycle input to guarantee a clean 50% clock input 50% to 60% duty-cycle improves DLL performance Low/high duty cycles will stop the DCM working See data sheet for specs

37. Divide-by-2 in Clock Wizard (from General Setup window)

38. Lesson Eight 622 Mbps Interface: Pulling it all together

39. Spartan-3 DCM Errata CLK2X feedback Fixed on XC3S50 and XC3S1000 Coming on remainder of Spartan-3 family in 2005 Negative phase shift (No longer an issue) Maximum DLL frequency in High Frequency mode

40. Problem Statement We want to build a LVDS transmitter operating at 622 Mbps with a 311 MHz input clock Issues: Probably NONE DCM not required as long as the input clock has roughly 50% duty cycle Transmitter macros with embedded FIFO are available for the Spartan-3 in 4:1, 6:1, 7:1 and 8:1 SERDES factors Transmitter macros are also available without the FIFO for designs that use the DCM

41. 622Mbit/second DDR Transmitter Example Clock output shown – data outputs are similar BUFG BUFG D0 D1 CE C0 C1 Q FDDRCPE OBUFDS 311 MHz FPGA IBUFGDS_DIFF_OUT 311 MHz 100 W No resistors required for differential transmitters.

42. Problem Statement We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock Issues: We have and need a 311 MHz clock We need phase shifting, which requires the DLL It is a DDR application Worry about jitter and duty-cycle distortion MISSION IMPOSSIBLE?

43. Typical 622 Mbps DDR DCM Configuration CLK0 CLK180 CLKFB CLKIN Phase shift control 311 MHz Exceeds DLL maximum frequency 311 MHz Exceeds DLL maximum phase shift frequency of 165 MHz DDR interface uses half-rate clock

44. Fundamental Problem 311 MHz forwarded clock coming right at us! Spartan-3 DCM supports shifting if CLKIN ≤ 165 MHz What to do? Use the dedicated divide by 2 option at the input of the DCM Clock applied to the DLL in the DCM will be 155.5 MHz Guarantees 50% duty-cycle  DCM Friendly! Phase shifting is performed with DCM in low-frequency mode Use the 2X and 2X180 DCM outputs to reproduce to the required 311 MHz once phase shift has been applied

45. Example 622 Mbps DDR DCM Configuration CLK2X CLK2X180 CLKFB CLKIN Phase shift control CLKIN_DIVIDE_BY_2=TRUE 311 MHz Clock double reproduces original input frequency 311 MHz Reduces 311 MHz incoming clock to <165 MHz, placing DCM in low-frequency mode Because input clock is 311 MHz and further reduced with optional divide-by-2, DCM support phase shifting DDR interface uses half-rate clock CLK2X output supports up to 330 MHz! NOTE: Double jitter as well Some devices require additional BUFG due to CLK2X feedback errata

46. CLK0 DCM CLK2X CLKIN CLKFB BUFG BUFG CLK2X180 CLKIN_DIVIDE_BY_2= TRUE CLK_FEEDBACK= 1X DLL_FREQUENCY_MODE= LOW 155.5 MHz 311 MHz BUFG The CLKIN_DIVIDE_BY_2 option reduces the effective DCM frequency to 155.5 MHz, which is within the DCM’s frequency limits. IBUFDS Phase shifter operates at up to 165 MHz. D CE C FDCPE Q D CE C FDCPE_1 Q CLK2X, CLK2X180 outputs limited to 330 MHz, maximum. CLK0 feedback required for specific part numbers. Optionally, use general-purpose interconnect but phase alignment not guaranteed. 622 Mbps 100 W LVDS/RSDS receiver termination resistor. FPGA IBUFGDS 311 MHz 100 W DETAILED VIEW

47. Problem Re-Statement We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock Issues solved : Phase shifting is indirectly available at 311 MHz Receiver macros are available for Spartan-3 at 1:4, 1:6, 1:7 and 1:8 SERDES factors Setup and hold ‘eye’ parameters do still require characterization

48. XAPP462: The DCM Reference A comprehensive 68-page “tree killer” Updated for ISE 6.3i and latest Spartan-3 DCM knowledge www.xilinx.com/bvdocs/appnotes/xapp462.pdf

49. Questions? [email protected]

50. Please Fill Out and Return the Feedback Forms! Steve Knapp Secrets of the DCM: Part 2 ü ü ü Forms are in the back of your FAE conference book Please return at back of the room Thank You!

51. Jump Point Return to last slide viewed Lesson 4: Phase Shifting Lesson 5: Frequency Synthesis Lesson 6: System vs. Source Synchronous Lesson 7: Optional CLKIN divide-by-2 Lesson 8: Spartan-3 622Mbps Design Example Session Evaluation Forms