Secrets of the DCM___________________.ppt

Secrets of the DCM

1. Secrets of the
DCM: Part 1
Steve Knapp
General Products Division
([email protected])
(v1.2, 11-OCT-2004)
© 2004 by Xilinx, Inc. All rights reserved.
スティーブ・ナップ
NOTICE:
This is an early draft of this presentation.
Please visit the Xilinx Sales Partner Web
(SPW) for the latest version.
http://www.partner.xilinx.com/common/spartan3/faeconf.htm

2. Secrets of the DCM (Part I) 2
Workshop Objectives
•Understand the function and application of Digital
Clock Managers (DCMs)
•Unlock a few mysteries on how DCMs operate
–More mysteries revealed in Part II
•Become a Clock Wizard and easily configure a DCM
•Have a few new approaches to teach customers on
DCMs
•Legitimately say “DCMs Don’t Confuse Me”
By the end of this class, you will …

3. Secrets of the DCM (Part I) 3
Real-World Experience
Up the Learning Curve
What’s a DCM?
Time
E
x
p
e
r
t
is
e
Part I
Part II

4. Secrets of the DCM (Part I) 4
DCMs Everywhere!
•In this presentation, the Spartan-3 DCM
demonstrates basic principals and concepts
•The Spartan-3 DCM is similar to Virtex-II and
Virtex-II Pro
•The DLL in the DCM is similar to the DLL in
Virtex/E and Spartan-II/E
•Virtex-4 DCM also employees similar concepts

5. Secrets of the DCM (Part I) 5
DCMs: The Clock
Problem Solver
Eliminate clock skew—improved performance!
Multiply or divide an incoming clock or create a
completely new clock frequency
Phase shift a clock
Condition a clock input to create 50% duty cycle
Any or all of the above, simultaneously!
 Don’t need it? Then don’t use it!

6. Secrets of the DCM (Part I) 6
DCM, Where Are You?
Block RAM
Column
DCM_X1Y1
DCM_X1Y0DCM_X0Y0
DCM_X0Y1
Global buffer multiplexers
Embedded
Multiplier
Column
Global buffer multiplexers
XC3S50 only
•Located at top and bottom of
block RAM/multiplier
column(s)
•Four DCMs in each Spartan-
3, except XC3S50, which has
two DCM
•DCMs have direct
connections to global buffers
along the same edge
•Each DCM has a unique
location string
–Watch PAR placement!

7. Secrets of the DCM (Part I) 7
DCM
DCM Block Diagram
Digital
Frequency
Synthesizer
Phase Shifter (PS)
In
p
u
t S
ta
g
e
O
u
tp
u
t S
ta
g
e
D
e
la
y
T
a
p
s
Status Logic
Delay-Locked Loop
(DLL)
PSINCDEC
PSEN
PSCLK
CLKIN
CLKFB
RST
PSDONE
STATUS[7:0]
LOCKED
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
Up to all nine clock
outputs available
simultaneously
Any four of nine
clock outputs
optionally connect to
global buffers along
same edge

8. Lesson One
Avoid being
skewed!

9. Secrets of the DCM (Part I) 9
The Ideal World
Other
Device on
Board
FPGA
A
B
C
A
B
C
SKEW

10. Secrets of the DCM (Part I) 10
In the Real World, You’re Skewed
Other
Device on
Board
A
FPGA
A
B
B
C
C
Dc
Db
Dc
Db
Two different timing relationships!

11. Secrets of the DCM (Part I) 11
No Skew, No Problem
Symbol -4
T
IOCKP 1.72 ns
Q
CLK
CLK
Q
Flip-flop Delay

12. Secrets of the DCM (Part I) 12
Skew: The Time Thief
CLK
Q
Input Buffer
Clock Distribution
Flip-flop
Symbol -4
T
IOCKP
1.72 ns
T
ICKOF
4.56 ns
Q
CLK

13. Secrets of the DCM (Part I) 13
Quick Review: What We Want
Other
Device on
Board
FPGA
A
B
C
A
B
C

14. Secrets of the DCM (Part I) 14
How Do We Get There?
Other
Device on
Board
A
B
C
A
B
C
c
b
What if we provide advance clocks?

15. Secrets of the DCM (Part I) 15
A
B
C
Db
Dc
The Answer?
Clairvoyant Logic, Of Course!
Other
Device on
Board
A
B
C
Db
Dc
-Db+ Db = NO SKEW!

16. Secrets of the DCM (Part I) 16
Houston, We Have a Problem
•First Rule of Time Travel: You can’t go backwards!
•Clairvoyant logic does not exist (well, at least not yet)
•Now what!?!

17. Secrets of the DCM (Part I) 17
Forward Thinking
Other
Device on
Board
A
B
C
A
B
C
bD
Dc
Delay=T- Dc
Delay=T - Db
Clock Period (T)

18. Secrets of the DCM (Part I) 18
The Tough Questions
•How do you specify the clock period?
•How do you determine the delays for Db and Dc?
•How do you voltage- and temperature-
compensate the design?
You Don’t!
?

19. Secrets of the DCM (Part I) 19
Classroom Experiments
•Everyone please take out your Delay-Lock Loop (DLL)
simulators
LAB 1: Feedback, frequency and phase locking
LAB 2: Stable, monotonic clock

20. Secrets of the DCM (Part I) 20
The Magical Delay-Locked
Loop (DLL)
Delay Line
Clock
Feedback
Clock
Feedback
Too Early
Each of the 256
taps is between 30
to 60 ps
Phase
Detector
ADJUST
Delay matched Clock and Feedback path lengths

21. Secrets of the DCM (Part I) 21
The Magical Delay-Locked
Loop (DLL)
Phase
Detector
Delay Line
Clock
Feedback
Clock
Feedback
Perfect!
Delay tap settings updated periodically for temperature/voltage compensation
Update rate controlled by an internal attribute called FACTORY_JF
LOCKED

22. Secrets of the DCM (Part I) 22
Resulting Timing
Symbol Description -4
T
IOCKPOutput flip-flop clock-to-output1.72 ns
T
ICKOFPin-to-pin clock-to-output delay, no DCM4.56 ns
T
ICKOFDCMPin-to-pin clock-to-output delay, with
DCM deskew
1.52 ns
•~ 3 ns eliminated from clock distribution delay
when using internal feedback!
•Output delay nearly completely eliminated when
using external feedback

23. Secrets of the DCM (Part I) 23
Locking
•The DLL requires a stable monotonic clock input
–Stable clock frequency
–Minimal jitter
•The DCM LOCKED output indicates when the DCM has
acquired and locked to the incoming clock
–Application should ignore the DCM clock outputs until LOCKED
asserted
•No clock edges can be missing during the locking process
•If clock is not yet stable, hold the DCM in reset
–External enabled oscillators
–External frequency scaling
–Cascaded DCMs

24. Secrets of the DCM (Part I) 24
Locking Process
FPGA Configuration
Startup Phase
LOCKED output
is LOW
Phase
aligned?
Output clocks
good?
LOCKED output
is HIGH
Lost lock.
LOCKED output
is LOW
Is CLKIN
stable? Within
specified limits?
RST Input
Asserted
Y
N
Y
N
FPGA application
asserts RST input
If CLKIN not yet stable,
assert RST input until
CLKIN stabilizes.
If lock is lost, assert RST
input to force DCM to
reacquire lock.

25. Secrets of the DCM (Part I) 25
LOCKED and STATUS Bits
•LOCKED (Output clocks good)
–The DCM clock outputs are not valid until LOCKED=1
–If LOCKED  0, reset the DCM (hit delay tap limits)
–It is possible for LOCKED=1 but the output clocks are invalid
–STATUS bits provide additional detail
•STATUS[1] – CLKIN Stopped
–STATUS[1]=1 if CLKIN stops toggling, reset the DCM
•STATUS[2] – CLKFX, CLKFX180 Stopped
–STATUS[2]=1 if CLKFX or CLKFX180 outputs stop, and these
outputs are used in the design, reset the DCM

26. Secrets of the DCM (Part I) 26
Feedback from a Reliable Source
•DLL requires feedback from one of two DCM
outputs
–CLK0 (1X feedback)
–CLK2X (2X feedback)
•CLK2X not presently available on all devices
–Presently supported only on XC3S50 and XC3S1000
–Coming to the remainder of the family in 2005
–Not supported in Virtex-II Pro

27. Secrets of the DCM (Part I) 27
DCMs Integrate into
FPGA Clock Path
IBUFG BUFG
PAD
IBUFG BUFG
PAD
CLKIN
CLKFB
CLKx
DCM

28. Secrets of the DCM (Part I) 28
Internal Feedback
I O
BUFG
Clock to
internal
FPGA logic
(or BUFGMUX,
or BUFGCE)
(Internal Feedback)
(alternate clock inputs
possible, but not fully
skew adjusted)
I O
IBUFG
CLKIN CLK0
CLKFB LOCKED
DCM
(or CLK2X)

29. Secrets of the DCM (Part I) 29
External Feedback
CLKIN CLK0
CLKFB LOCKED
DCM
(or CLK2X)
I O
OBUF
I O
OBUF
FPGA
Other
Device(s)
on Board
CLK
ENABLE
(External Feedback Trace)
Circuit-board trace
delay, additional
clock buffers, etc.
RESETD
WCLK
A[3:0]
Q
INIT=000F
SRL16
I O
IBUFG
I O
IBUFG
Delay matched Clock and Feedback path lengths

30. Secrets of the DCM (Part I) 30
Clock Wizard Makes it Easy!

31. Lesson Two
Wizard School

32. Secrets of the DCM (Part I) 32
DCM Rules and Lots of Them
The DFS accepts input clock
frequencies down to 1 MHz if you
are not using the Delay-Locked
Loop (DLL)
T
h
e
D
L
L
o
u
tp
u
ts
o
p
e
ra
te
u
p
to

2
8
0
M
H
z
u
n
le
s
s
y
o
u
u
s
e
p
h
a
s
e

s
h
iftin
g
, th
e
n
th
e
m
a
x
im
u
m

fre
q
u
e
n
c
y
is
1
6
5
M
H
z
The CLK90 and
CLK270 outputs are
only available
when the DLL is in
low-frequency mode
The minimum DLL output
frequency must be 24 MHz
or greater
The DLL feedback must come
from either CLK0 or CLK2X.
The CLK2X feedback does not
work for all devices
The variable phase shifter uses
the PSEN, PSINCDEC, PSCLK,
PSDONE, and STATUS bits
The output jitter on the CLKFX and
CLKFX180 output depends on the
DFS Multiply and Divide settings
A
n
y
fo
u
r o
f th
e
n
in
e
p
o
s
s
ib
le

D
C
M
o
u
tp
u
ts
c
a
n
c
o
n
n
e
c
t to

g
lo
b
a
l c
lo
c
k
b
u
ffe
rs
The CLKDV output
can only divide the
incoming clock by
certain values
The frequencies supported by the
DFS may be limited by the DLL if
used within the same DCM
The DLL requires that the
CLKFB input be connected.
The DFS does not require
feedback
The amount of phase shift
may be limited due to the
incoming clock frequency

33. Secrets of the DCM (Part I) 33
DCM Rule #1
•All DCMs in a design
must be instantiated
•Language Templates
available in ISE
•Clock Wizard makes it
easy
CLKIN CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
STATUS[7:0]
LOCKED
PSDONE
CLKFB
RST
PSEN
PSINCDEC
PSCLK
DCM
DSSEN

34. Secrets of the DCM (Part I) 34
Schematic of DCM Example
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
STATUS
LOCKED
PSDONE
CLKIN
CLKFB
RST
PSEN
PSINCDEC
PSCLK
DCM
IBUFG BUFG
BUFG
33 MHz
33 MHz
3.3 MHz
CLK_FEEDBACK = 1X
CLKDV_DIVIDE = 10
CLKFX_MULTIPLY = 29
CLKFX_DIVIDE = 11
CLKOUT_PHASE_SHIFT = VARIABLE
DFS_FREQUENCY_MODE = LOW
DLL_FREQUENCY_MODE = LOW
PHASE_SHIFT = 23
87 MHz

35. Secrets of the DCM (Part I) 35
ISE 6.3i Clock Wizard
Clock Wizard
Graphically configure a
Digital Clock Manager
(DCM)
Vendor-specific
VHDL or Verilog
VHDL or Verilog
instatiation
template
Xilinx Architecture
Wizard (XAW)
settings file
User constraints
file (UCF)
Greatly simplifies using a DCM!

36. Secrets of the DCM (Part I) 36
Two Methods to Invoke
Clock Wizard
•From Window Start menu
–Start  Xilinx ISE 6  Accessories 
Architecture Wizard
•From within Project Navigator
–Project  New Source

37. Secrets of the DCM (Part I) 37
Project Navigator Method
New Source
User Document
Schematic
VHDL Library
VHDL Package
VHDL Test Bench
Test Bench Waveform
BMM File
MEM File
Implementation Constraints File
IP (CorGen & Architecture Wizard)
State Diagram
My_Spartan-3
File Name:
MyDirectory
Location:
...
Add to Project
< Back Next > Cancel Help
Enter the filename to
save the settings for this
DCM module
Click here to select the
directory for the
filename
Click Next to
continue
Choose IP (CoreGen &
Architecture Wizard)
VHDL Module

38. Secrets of the DCM (Part I) 38
Selecting the Right Wizard
Architecture Selection Wizard
Architecture Wizards for Spartan-3
Clocking Wizard
Single DCM
Clock Forwarding / Board Deskew
Board Deskew with an Internal Deskew
Clock Switching with Two DCMs
Cascading in Series with Two DCMs
Select the wizard:
OK Cancel
(a) Architecture Wizard Accessory
Select Core Type
Basic Elements
Clocking
Cascading in Series with Two DCMs
Board Deskew with an Internal Deskew
Clock Forwarding / Board Deskew
Clock Switching with Two DCMs
Communications & Networking
Digital Signal Processing
< Back Next > Cancel Help
Single DCM
Architecture Wizard: Single DCM
(b) IP (CoreGen & Architecture Wizard)

39. Secrets of the DCM (Part I) 39
General Setup
Xilinx Clocking Wizard - General Setup
Input Clock Frequency
MHz ns33
Advanced ...
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLKFX
CLKFX180
LOCKED
STATUS
PSDONE
CLKIN
CLKFB
RST
PSEN
PSINCDEC
PSCLK
More Info
< Back Next > Cancel
Check CLKFX or
CLKFX180 to enable the
Frequency Synthesizer
options
Check CLKDV to enable
the Clock Divider options
Enter input clock
frequency, with
full accuracy, in
MHz or ns
Click here for help
on this screen
Click here for
advanced options
When checked, the CLK0,
CLK90, CLK180, and
CLK270 outputs have 50%
duty cycle
Click Next to
continue
DCM attribute name
10
Divide By Value
CLKDV_DIVIDE
Value:
Phase Shift
PHASE_SHIFT
23
VARIABLE
Type:
2.695 ns32.344 Degrees
CLKIN Source
InternalExternal
Single
Differential
DLL_FREQUENCY_MODE
DUTY_CYCLE_CORRECTION
1X 2X
Feedback Value
CLK_FEEDBACK
Feedback Source
InternalExternal None
Single
Differential
Use Duty Cycle Correction
CLKOUT_PHASE_SHIFT
Selecting External
automatically connects
CLKIN to an IBUFG global
buffer input primitive.
Select Internal to connect
CLKIN to another source.
Select Fixed to phase shift
all outputs by the value
defined below. Select
Variable mode to
dynamically adjust phase
shifting using the PSEN,
PSINCDEC, and PSCLK
inputs.
Sets the Fixed phase shift
value or the initial value for
Variable phase shift mode,
measured as x/256ths of a
clock period, where x=0 to
255.
Indicate whether the
feedback is from an
Internal or External source
or None
If clock feedback is
required, is it from the
CLK0 output (1X) or the
CLK2X output (2X)?
If clock or feedback is
External, choose whether
the input is Single-ended or
Differential
Set the frequency divider for
the Clock Divider output,
CLKDV

40. Secrets of the DCM (Part I) 40
Assigning Global Buffers
Xilinx Clocking Wizard - Clock Buffers
Clock Buffer Settings
Use Global Buffers for all selected clock outputs
Customize buffers
More Info
< Back Next > Cancel
By default, Clock
Wizard places
global buffers
(BUFG) on all the
selected DCM
clock outputs
Optionally,
customize how the
DCM clock outputs
connect to the
other FPGA logic
using the grid
below
Click here for help on
this screen
Click Next to
continue
Add Buffer
Input I0 Input I1 View/Edit Buffer
Global BufferCLK0
Enabled BufferCLK90
Clock MuxCLK180
Local RoutingCLK270
LowskewlineCLKDV
For each clock
output, select the
type of buffer
connecting the
signal to the
FPGA
CLK90
BUFG
I0 O
BUFGCE
I0 O
CE
O
S
BUFGMUX
I0
I1
I0
I0
Global Buffer
Enabled Buffer
Clock Mux
Local Routing
Lowskewline

41. Secrets of the DCM (Part I) 41
Frequency Synthesizer
CLK0
CLKFX
CLKFX180
Check CLKFX or
CLKFX180 to enable
the Frequency
Synthesizer options
If using only the
CLKFX or CLKFX180
clock outputs, uncheck
CLK0 to extend the
DCM frequency limits
Source:
Feedback
Internal External None
Value: 1X 2X
If only using the CLKFX or CLKFX180
clock ouputs, optionally click None to
extend the DCM frequency limits.
(back on General Setup)
Xilinx Clocking Wizard - Clock Frequency Synthesizer
Inputs for Jitter Calculations
Use output frequency
MHz ns87
Use Multiply (M) and Divide (D) values:
4M 1D
Input Clock Frequency: 33.000 MHz
Calculate
< Back Finish Cancel
More Info
Enter the desired output
frequency, in MHz or ns,
then click Calculate. DCM
Wizard calculates the best
multiply (M) and divide (D)
values possible.
Optionally, enter the specific
values for the multiply (M)
and divide (D) values, then
click Calculate
Displays the incoming clock
frequency, specified earlier
Click Finish
when finished
DCM attribute name
CLKFX_MULTIPLY CLKFX_DIVIDE
DFS_FREQUENCY_MODE
Valid Ranges for Speed Grade -4
DFS
Low
High
Fin (MHz)
24.000 - 165.000
48.000 - 280.000
Fout (MHz)
24.000 - 210.000
210.000 - 280.000
M D Output
Frequency
(MHz)
Period Jitter
(unit interval)
Period Jitter
(pk-to-pk ns)
Generated Output
2911 87 0.10 1.12
After entering the desired
output frequency or multiply
and divide values, click
Calculate to compute the
resulting jitter for the
Frequency Synthesizer output
Displays the frequency limits
for the Frequency Synthesizer
in both low- and high-
frequency mode
Displays the calculated output
jitter values based on the
settings
Click here for help on
this screen
CLKFX_MULTIPLY CLKFX_DIVIDE

42. Secrets of the DCM (Part I) 42
Voila!

43. Secrets of the DCM (Part I) 43
Instantiation Template
Module View
COMPONENT my_dcm
PORT (
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
LOCKED_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
Inst_my_dcm: my_dcm PORT MAP(
CLKIN_IN => ,
RST_IN => ,
LOCKED_OUT => ,
CLK0_OUT =>
);
xc3s400-4fg456
My_Design (my_design.vhd)
my_dcm (my_dcm.xaw)
Process View
Sources in Project:
Add Existing Source
Create New Source
Create Schematic Symbol
View HDL Source
View HDL Instantiation Template
Processes for Source: “my_dcm”
Click new Clock
Wizard source file
Double click to view
instantiation template
VHDL
component
declaration
VHDL
component
instantiation
Available for both VHDL and Verilog
VHDL Example

44. Lesson Three
Jitter

45. Secrets of the DCM (Part I) 45
What is Jitter?
•Uncertainty on exact timing of a clock edge
•Affected by power noise, decoupling, SSOs, internal
switching, etc.
•Period (peak-to-peak) jitter specification is most quoted
–Specified as either absolute (300 ps) or deviation (± 150 ps)
Ideal Clock
Measured clock period
N
u
m
b
e
r
o
f

s
a
m
p
l
e
s
Peak-to-peak Period Jitter

46. Secrets of the DCM (Part I) 46
Clock Jitter Specifications
•Period (peak-to-peak) jitter
•Cycle-to-cycle jitter
•Unit Interval (UI)
T
1
=T
0
+100 ps T
2
=T
1
-150 psT
0
Bit Period
Peak-to-peak
Period Jitter
Unit Interval (UI)Peak-to-peak period jitter,
represented as fraction of
Unit Interval
Example
UI=0.10 means that
period jitter is 10% of
the total bit period

47. Secrets of the DCM (Part I) 47
Half
Period
Jitter
Jitter Effects on Cycle Timing
Bit Period
Single Data Rate (SDR)
Available Period
Earliest
Arrival
Clock Period

48. Secrets of the DCM (Part I) 48
Jitter Effects on Cycle Timing
Double Data Rate (DDR)
Clock Period
No duty-cycle distortion
effects considered
Earliest
Arrival
Bit Period
Consider both clock
edges in DDR
applications
Available
Period
Jitter
Available
Period

49. Secrets of the DCM (Part I) 49
Jitter Effects on Flip-Flop Timing
Early Clock Edge Late Clock Edge
•Increases input set-up time
•Reduces minimum clock-to-
output time
•Increases hold time
•Increases maximum clock-to-
output time
Half
Period
Jitter
Half
Period
Jitter

50. Secrets of the DCM (Part I) 50
Minimizing Clock Jitter
•Switching noise causes jitter
–Proper power, PCB design, and decoupling
•XAPP623: Power System Distribution Guidelines
http://www.xilinx.com/xapp/xapp623.pdf
•PCB Checklist
http://support.xilinx.com/products/design_resources/highspeed_design/si_pcbcheck.htm
–% CLB switching contributes noise
–Obey SSO recommendations (in Spartan-3 data sheet)
•VCCAUX is voltage source for DCMs
•GND pins for logic and DCMs are common
•Jitter on input clock
–Garbage in, garbage out
•Take care of your clocks and your clocks will take care of you

51. Secrets of the DCM (Part I) 51
GOVERNMENT HEALTH WARNING:
FAILING TO APPLY XAPP623 COULD BE
HAZARDOUS TO YOUR DCM DESIGN AND
YOUR MENTAL HEALTH

52. Secrets of the DCM (Part I) 52
XAPP462: The DCM Reference
•A comprehensive 68-
page “tree killer”
•Updated for ISE 6.3i and
latest Spartan-3 DCM
knowledge
www.xilinx.com/bvdocs/appnotes/xapp462.pdf

53. Secrets of the DCM (Part I) 53
Second Verse, Same as the First*
•If you enjoyed this session, please also attend …
* Only a little bit louder and a whole lot worse
Secrets of the DCM
Part II

54. Secrets of the DCM (Part I) 54
Questions?
[email protected]

55. Secrets of the DCM (Part I) 55
Please Fill Out and Return the
Feedback Forms!
Steve Knapp
Secrets of the DCM: Part 1
ü
ü
ü
•Forms are in the back of your FAE conference book
•Please return at back of the room
Thank You!

56. Secrets of the DCM (Part I) 56
Jump Point
Return to last slide viewed
• Overview
• Lesson 1: Avoid Being Skewed
• Lesson 2: Clock Wizard School
• Lesson 3: Clock Jitter
• Session Evaluation Forms