solid state electronics ktu module 5 slides

solid state electronics

1. EC203 SOLID STATE DEVICES

2. MODULE V
MOSFETscaling–needforscaling,constantvoltagescalingandconstantfield
scaling,SubthresholdconductioninMOS.Shortchanneleffects-Channellength
modulation,DrainInducedBarrierLowering,VelocitySaturation,ThresholdVoltage
VariationsandHotCarrierEffects.Non-PlanarMOSFETs:FinFET–Structure,
operationandadvantages

3. MOSFET scaling –need for scaling
•DesignofhighdensitychipinMOSVLSItechnologyrequiresthatpackingdensityshould
increase,accordinglysizeoftheICmustdecrease.
•Thereductionofthesize,i.e.,thedimensionsofMOSFETs,iscommonlyreferredtoas
scaling.
•ScalingofMOStransistorsisconcernedwithsystematicreductionofoveralldimensions
ofthedevices.
•Theproportionalscalingofalldevicesinacircuitwouldcertainlyresultinareductionof
thetotalsiliconareaoccupiedbythecircuit,therebyincreasingtheoverallfunctional
densityofthechip.
•Therearetwobasictypesofsize-reductionstrategies:
✓Fullscaling(Constant-fieldscaling)
✓Constantvoltagescaling
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

4. CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

5. Motivation for Scaling
•More transistors --> Higher performance
•Less delay time --> Higher frequency
•Less V
DD--> Lower power consumption
Nanoelectronics:Anoverview by Dr.SanthanuMahapatra

6. Full Scaling (Constant-Field Scaling)
•PreservethemagnitudeofinternalelectricfieldsintheMOSFET,whilethe
dimensionsarescaleddownbyafactorofS.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

7. Influence of scaling
•The gate oxide capacitance per unit area, on the other hand, is changed
•Aspect ratio WIL will remain unchanged under scaling.
•Trans conductance parameter k
nwill be scaled by a factor of S.
•Linear-mode drain current of the scaled MOSFET
•Saturation-mode drain current is reduced by the scaling factor.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

8. •Power dissipation of the transistor will be reduced by the factor s
2
.
•Gate oxide capacitance scaled down by a factor of s.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

9. Constant-Voltage Scaling
•Thepowersupplyvoltageandallterminalvoltagesbescaleddownproportionallywith
thedevicedimensions.
•Constant-voltagescalingisusuallypreferredoverfullscaling-Peripheralandinterface
circuitrymayrequirecertainvoltagelevelsforallinputandoutputvoltages,whichin
turnwouldnecessitatemultiplepowersupplyvoltagesandcomplicatedlevelshifter
arrangements.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

10. Influence of constant voltage scaling
•AlldimensionsoftheMOSFETarereducedbyafactorofS.
•Powersupplyvoltageandtheterminalvoltagesremainunchanged.
•Dopingdensitiesmustbeincreasedbyafactorofs
2.
•GateoxidecapacitanceperunitareaC
oxisincreasedbyafactorofS,whichmeans
thatthetransconductanceparameterisincreasedbyS.
•LinearmodedraincurrentofthescaledMOSFET
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

11. CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

12. •Saturation current of the device
•Power dissipation of the MOSFET increases by a factor of S.
•Power density (power dissipation per unit area) is found to increase by a factor of S
3
.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

13. Difference between full scaling and constant voltage scaling

14. Long-channel devices
oWidth and length long enough so that edge effects from
the four sides can be neglected
oChannel length L must be much greater than the sum of
the drain and source depletion widths
Short channel devices
oWidth and length short enough such that the edge
effects can not be neglected
oDevices with width and length short enough such that the
edge effects can not be neglected
14
https://people.rit.edu/lffeee/mosfet_s.pdf

15. Sub threshold conduction in MOS
•AsperdraincurrentexpressionI
D=0whenV
G=V
T.
•Thereissomedrainconductionbelowthreshold-subthresholdconduction.
•Thiscurrentisduetoweakinversioninthechannelbetweenflatbandandthreshold(for
bandbendingbetweenzeroand2φ
F),whichleadstoadiffusioncurrentfromsourceto
drain.
Where
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

16. •I
Ddependsexponentiallyongatebias,V
G.
•V
DhaslittleinfluenceonI
DonceV
DexceedsafewkT>q.
•TheslopeofI
D-V
GScurveisknownasthesubthreshold
slope,S.
•Ithastypicalvaluesof70mV/decadeatroom
temperature
•AchangeintheinputV
Gof70mVwillchangetheoutput
I
Dbyanorderofmagnitude.
•SmallerthevalueofS,thebetterthetransistorisasa
switch.
•AsmallvalueofSmeansasmallchangeintheinputbias
canmodulatetheoutputcurrentconsiderably.
•S is a measure of the efficacy of the gate potential in
•modulating I
D.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

17. Short Channel Effects
•AMOStransistoriscalledashort-channeldeviceifitschannellengthisonthe
sameorderofmagnitudeasthedepletionregionthicknessesofthesourceand
drainjunctions.
•IftheeffectivechannellengthL
effisapproximatelyequaltothesourceanddrain
junctiondepthx.
•Effects
(i)Limitationsimposedonelectrondriftcharacteristicsinthechannel
(ii)Modificationofthethresholdvoltageduetotheshorteningchannellength.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

18. Velocity Saturation
•Astheeffectivechannellengthisdecreases,lateralelectricfieldE
Yalongthechannel
increases
•Atlowfield:ElectrondriftvelocityV
dinthechannelisproportionaltotheelectricfield
•Athighfield:Driftvelocitytendstosaturate
•AsE=10
5
V/cmandhigher,theelectrondriftvelocitysaturatestovalueofaboutv
d(sat)=
10
7
cm/s.
•Carriervelocitysaturationactuallyreducesthesaturation-modecurrent
•Thecurrentisnolongeraquadraticfunctionofthegate-to-sourcevoltageVGS,anditis
virtuallyindependentofthechannellength
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

19. Mobility Degradation
•Inshort-channelMOStransistors,thecarriervelocityinthechannelisalsoa
functionofthenormal(vertical)electric-fieldcomponentE
x.
•Verticalfieldinfluencesthescatteringofcarriers(collisionssufferedbythe
carriers)inthesurfaceregion,thesurfacemobilityisreducedwithrespecttothe
bulkmobility
•Itisgivenbytherelation
•µ
noisthelow-fieldsurfaceelectronmobilityandϴisanempiricalfactor.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

20. Threshold Voltage Variations
•Inshort-channelMOStransistors,n+drainandsourcediffusionregionsinthep-
typesubstrateinduceasignificantamountofdepletioncharge.
•Long-channelthresholdvoltageexpressionoverestimatesthedepletioncharge
supportedbythegatevoltage.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

21. •Thedraindepletionregionislargerthanthesourcedepletionregionbecausethe
positivedrain-to-sourcevoltagereverse-biasesthedrain-substratejunction.
•Significantportionofthetotaldepletionregionchargeunderthegateisactuallydue
tothesourceanddrainjunctiondepletion,ratherthanthebulkdepletioninducedby
thegatevoltage.
•Thethresholdvoltageexpressionmustbemodifiedtoaccountforthisreduction.
•∆V
T0isthethresholdvoltageshift(reduction)duetotheshort-channeleffect.
•Thereductiontermactuallyrepresentstheamountofchargedifferentialbetweena
rectangulardepletionregionandatrapezoidaldepletionregion.
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

22. •Let ∆ L
S and ∆ L
Drepresent the lateral extent of the depletion regions associated
with the source junction and the drain junction
•Let x
dsand x
dDrepresent the depth of the pn-j unction depletion regions
associated with the source and the drain
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

23. •From figure
•On solving for ∆L
D
•Similarly
•The amount of threshold voltage reduction AV70 due to short-channel effects
CMOS Digital Integrated Circuits, Analysis And Design,sung-moKang, Yusuf Leblebigi,secondDition

24. •Asthechannellengthsarereduced,thesharedchargebecomesalargerfraction
ofthetotal,andthisresultsinaV
Troll-offasafunctionofL.
•Narrow width effect, where the V
T goes up as the channel width Z is reduced for
very narrow devices.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

25. Drain Induced Barrier lowering
•Unintended electrostatic interactions between the source and the drain is known
as Drain-InducedBarrier Lowering (DIBL).
•It may occur if
•Small channel length MOSFETs are not scaled properly
•Source/drain junctions are too deep or the channel doping is too low
•This leads to punch-throughleakage or breakdown between the source and the
drain, and loss of gate control.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

26. •As the drain bias is increased, the conduction band
edge inthe drain is pulled down.
•The drain-channeldepletion width expands.
•For a long channel MOSFET, the drain bias does
not affect the source-to-channelpotential barrier,
which corresponds to the built-inpotential of the
source-channelp-njunction.
•Hence, unless the gate bias is increased to lower
this potential barrier, there is little drain current.
•For a short channelMOSFET, as the drain bias is
raised and the conduction band edge in the drain
is pulled down.
•The source-channelpotential barrier is lowered
due to DIBL.
•There can be significant drain leakage current, with
the gate being unable to shut it off.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

27. •Solutions
•The source/drain junctions must be made sufficiently shallow (i.e., scaled properly)
as the channel lengths are reduced, to prevent DIBL.
•Secondly, the channel doping must be made sufficiently high to prevent the drain
from being able to control the source junction.
•Anti-punch-throughimplant in the channel
•Instead of implant throughout the channel a localized implant is done only near the
source/drains. These are known as halo or pocket implants.
•The higher doping reduces the source/drain depletion widths and prevents their
interaction.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

28. Channel length modulation
➢Assumption:Draincurrentisconstantin
saturationregion
➢AsV
dsincreasespinchoffregionextendsalong
thechannelawayfromdrain
➢Effectivechannellengthdecreases
➢I
d=µC
ox(W/L)(V
gs-V
th)
2
➢TransistorcurrentincreasesasL
effdecreases
28Analog VLSI: Circuits and Principles By Shih-ChiiLiu( ) ( ) 
satDDSTHGSoxnsatD VVVV
L
W
CI
,
2
, 1
2
1
−+−= 

29. Channel length modulation Continued……….
29
www-inst.eecs.berkeley.edu/~ee105/fa07/lectures/Lecture%2017.ppt

30. 30
CmosDigital Integrated Circuits By Sung-Mo Kang, Yusuf Leblebici

31. •ForshortchannelMOSFETs,DIBLisrelatedtotheelectricalmodulationofthe
channellengthinthepinch-offregion,L.
•Sincethedraincurrentisinverselyproportionaltotheelectricalchannellength
•Thefractionalchangeinthechannellengthisproportionaltothedrainbias
whereλisthechannellengthmodulationparameter
•Draincurrentismodifiedas
Channel length modulation
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

32. Hot Electron Effects
•Ifwesimplyreducedthedimensionsofthedeviceandkeptthepowersupply
voltagesthesame,theinternalelectricfieldsinthedevicewouldincrease.
•Foridealscaling,powersupplyvoltagesshouldalsobereducedtokeeptheinternal
electricfieldsreasonablyconstant.
•Inpractice,powersupplyvoltagesarenotscaledhand-in-handwiththedevice
dimensions,partlybecauseofothersystem-relatedconstraints.
•Thelongitudinalelectricfieldsinthepinch-offregion,andthetransverseelectric
fieldsacrossthegateoxide,increasewithMOSFETscaling.
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

33. Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

34. •Whenanelectrontravelsfromthesourcetothedrain
alongthechannel,itgainskineticenergy,andbecomesa
“hot”electron.
•Asitgainsmorekineticenergy,itmoveshigherupinthe
conductionband.
•Afewoftheelectronscanbecomeenergeticenoughto
surmountthepotentialbarrierbetweentheSichannel
andthegateoxide.
•Someoftheseinjectedhotelectronscangothroughthe
gateoxideandbecollectedasgatecurrent,thereby
reducingtheinputimpedance.
•Someoftheseelectronscanbetrappedinthegateoxide
asfixedoxidecharges.Thisincreasestheflatband
voltage,andthereforetheV
T.
•EnergetichotcarrierscanruptureSi–Hbondsthatexist
attheSi-SiO
2interface,creatingfastinterfacestatesthat
degradeMOSFETparameters.
•Solution:Lightlydopeddrainstructure
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

35. •Astheelectronstraveltowardthedrainandbecome
hot,theycancreatesecondaryEHPsbyimpact
ionization.
•Thesecondaryelectronsarecollectedatthedrain,and
causethedraincurrentinsaturationtoincreasewith
drainbiasathighvoltages,therebyleadingtoa
decreaseoftheoutputimpedance.
•Thesecondaryholesarecollectedatthesubstrateas
substratecurrent.
•Thiscurrentcancreatecircuitproblemssuchasnoiseor
latchupinCMOScircuits
Solid State Electronic Devices,seventhedition,Ben G. Streetman • Sanjay Kumar Banerjee

36. Ultra –Thin-Body MOSFET (Planar)
❑Control over short channel effects
❑Layered Silicon-Insulator-Silicon in place of
conventional Silicon
❑Lower junction leakage
❑Better electrostatic control reduce S-D leakage
❑For high density , high performance , low
power applications
36

37. Different device architectures
37

38. Double gate MOSFET (Non-Planar MOSFETs)
❑Second gate electrode at opposite side of silicon body
❑Two channels –Top & Bottom
❑Increased gate control
❑Advantages
✓Increased scalability
✓Lower junction capacitance
✓Larger drive current
❑Disadvantages
✓Higher series S/D resistance
✓Difficulty in fabrication
38

39. Continued….
39

40. FinFET(Non planar MOSFET)
•Also called tri-gate transistor.
•FinFETscan be implemented either on bulk
silicon or SOI wafer.
•This FinFETstructure consists of thin (vertical)
fin of silicon body on a substrate.
•The gate is wrapped around the channel
providing excellent control from three sides of
the channel.
•This structure is called the FinFETbecause its Si
body resembles the back fin of a fish.
Former TSMC CTO and Berkeley professor ChenmingHu and his team presented the concept of
FinFETin 1999
A Review Paper on CMOS, SOI and FinFETTechnology ByPavanH Vora, RonakLad (EinfochipsPvt. Ltd.)
Fig:FinFETStructure

41. Structure of FinFET
41

42. •Inbulk-MOS(plannerMOS),thechannelishorizontal.
•InFinFETchannel,itisvertical.
•ForFinFET,theheightofthechannel(Fin)determinesthe
widthofthedevice.
•Theperfectwidthofthechannelisgivenby
WidthofChannel=2XFinHeight+FinWidth
•ThedrivecurrentoftheFinFETcanbeincreasedby
increasingthewidthofthechanneli.e.byincreasingthe
heightoftheFin.
•Wecanalsoincreasethedevicedrivecurrentby
constructingparallelmultiplefinsconnectedtogether.
Fig: Multi fin FET Structure
A Review Paper on CMOS, SOI and FinFETTechnology ByPavanH Vora, RonakLad (EinfochipsPvt. Ltd.)

43. •FinFETWorking:ThemodeofoperationofaFinFETdoesnotdifferfromatraditionalfield
effecttransistor.Thereisonesourceandonedraincontactaswellasagatetocontrolthe
currentflow.
•InconventionalMOS,adopingisinsertedintothechannel,reducingthevariousSCEsand
ensuringhighV
th.
•WhileinFinFET,thegatestructureiswrappedaroundthechannelandthebodyisthin,
providingbetterSCEs,sochanneldopingbecomesoptional.
•ItimpliesthatFinFETsufferslessfromdopant-inducedvariations.
•Lowchanneldopingalsoensuresbettermobilityofthecarriersinsidethechannel.Hence,
higherperformance.
A Review Paper on CMOS, SOI and FinFETTechnology ByPavanH Vora, RonakLad (EinfochipsPvt. Ltd.)

44. Types of FinFET
Bulk FinFETs: Design at 14 nm Node and Key Characteristics Jong-Ho Lee 44

45. Bulk V/S SOI FinFET
Bulk FinFET SOI FinFET
Deep etching needed simpler fabrication
Need isolation no isolation problem
Cheaper Expensive
45

46. Advantages:
✓FinFEThas higher drive current.
✓Strain technology can be used to increase carrier mobility.
✓Improved transistor sub threshold swing due to greatly improved gate control.
✓Improved channel mobility due to reduced transverse electric field,
✓Reduced parasitic capacitances from the absence of depletion capacitances,
leading to improved speed,
✓Reduced power consumption
✓Much Lower off-state current compared to bulk counterpart.
Disadvantages:
oWidth quantization
oParasitic resistance is the main adverse factor which prevents FinFETs’ application,
which leads to lower speed and high noise.
oComplex manufacturing process
46
A Review Paper on CMOS, SOI and FinFETTechnology ByPavanH Vora, RonakLad (EinfochipsPvt. Ltd.)

47. TrigateFinFET
•An extension of the FinFETstructure, and
allows variable device widths
•Can have multiple fins connected
together to increase the total drive
strength
•It requires aggressive lithography
techniques.
47Image :https://www.semiwiki.com/forum/content/3591-intel-ansys-enable-14nm-chip-production.html