Switch level modeling 2 x4

SWITCH LEVEL MODELLING 2X4

1. Switch Level Modeling:-
The switch level of modeling provides a level of abstraction between the
logic and analog-transistor levels of abstraction, describing the
interconnection of transmission gates which are abstractions of
individual MOS and CMOS transistors. The switch level transistors are
modeled as being either on or off, conducting or not conducting. Further,
the values carried by the interconnections are abstracted from the whole
range of analog voltages or currents to a small number of discrete values.
These values are referred to as signal strengths.
NOT GATE NAND GATE


SYNTEX:-
Nmos n1(output,data,control)
Pmos p1(output,data,control)

2. DECODER
In digital electronics, a binary decoder is a combinational logic circuit that
converts binary information from the n coded inputs to a maximum of
2
n
unique outputs. They are used in a wide variety of applications, including
data DE multiplexing, seven segment displays, and memory address
decoding.

3. BLOCK DIAGRAM USING BASIC GATES:-




TRUTH TABLE:-

4. PROGRAM:-
module notgate1(x,y);
input x;
output y;
supply0 gnd;
supply1 vdd;
pmos x1(y,vdd,x);
nmos x2(y,gnd,x);
endmodule

module andgate(a,b,y);
input a,b;
output y;
wire w,w1;
supply0 gnd;
supply1 vdd;
pmos y1(w,vdd,a);
pmos y2(w,vdd,b);
nmos y3(w1,gnd,b);
nmos y4(w,w1,a);
notgate1 y5(w,y);
endmodule

module decoder(a,b,i);
input a,b;
output [3:0]i;
wire abar,bbar;
notgate1 z1(a,abar);
notgate1 z2(b,bbar);
andgate z3(abar,bbar,i[0]);
andgate z4(abar,b,i[1]);
andgate z5(a,bbar,i[2]);
andgate z6(a,b,i[3]);
endmodule

module decoder_test();
reg a,b;
wire [3:0]i;
decoder d1(a,b,i);
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
#5 $stop;
end
endmodule

5. WAVEFORM:-

6. SCHEMATIC DIAGRAM: -

7. PROGRAM IN CADENCE: -