switching theory and logical design for ece

ECE

1. EE505.35 to 36 1
Name of the faculty : M. HEMALATHA
Designation : Lecturer
Branch : ECE
Institute : GMR Govt. polytechnic,madanepally
Year/Semester : III Semester
Subject : Digital Electronics
Subject code : EE505
Major Topic : Sequential Logic Circuits
Duration : 100 min
Sub-topic : RS flip-flop, JK flip-flop
Teaching Aids : PPT
DEPARTMENT OF TECHNICAL EDUCATION
ANDHRA PRADESH

2. EE505.35 to 36 2
OBJECTIVES
On completion of this period, you would be able
to
•Understand RS Flip-flop construction and working.
•Know the use of SR latch as debouncing switch
•JK Flip-flop construction and working.

3. EE505.35 to 36 3
Recap
•What is a latch?
•What is meant by a flip-flop?
•Difference between a Flip-flop and latch.
•What are sequential circuits.

4. EE505.35 to 36 4
RS FLIP FLOP
S
Q
R Q
RS
FF
•A latch is similar to a Flip Flop.
•It can reside in either of two stable states.
•So NAND or NOR latches are also called “RS
Flip Flop”.
Logic symbol of RS Flip Flop is
Fig 1

5. EE505.35 to 36 5
Clocked RS Flip-flop
Clocked RS Flip Flop using NAND gates is shown in
the figure
S
R
CLK
S
Q
R
Q
RS
FF
CLK
Q
Q
Fig 2

6. EE505.35 to 36 6
Truthtable of clocked RS Flip-flop
INPUTS OUTPUTS
Mode of Operation
CLKR S Q Q OPERATION
0 0 0
NO
CHANGE HOLD
0 0 1
0 1 0
0 1 1
1 0 0 No Change Hold
1 0 1 1 0 SET
1 1 0 0 1 RESET
1 1 1
RaceRace prohibited
Race: The unpredictable state of output is known as Race

7. EE505.35 to 36 7
Timing diagram for a clocked RS Flip-flop
S
Q
R
CLK
Fig 3

8. EE505.35 to 36 8
SR Latch as debouncing switch
•SR latch can be used to eliminate mechanical switch
debounce.
•switch debounce occurs when the contacts of a mechanical
switch or keypad are operated and the switch contacts do not
fully close but bounce before closing,
•This gives a series of pulses that the electronic system or
circuit may see as a series of logic pulses Instead of one
single pulse and behave incorrectly.
•Flip-flops or bi-stable circuits are used to eliminate this
problem and this is shown Fig 4.

9. EE505.35 to 36 9
SR Latch as debouncing switch
Fig 4

10. EE505.35 to 36 10
•Depending upon the current state of the output, if the set or
reset pushbuttons are depressed the output will change
•Any additional unwanted inputs (bounces) from the
mechanical action of the switch will have no effect on the
output.
•When the other pushbutton is pressed, the very first contact
will cause the latch to change state, but any additional
bounces will also have no effect.
SR Latch as debouncing switch (contd.)

11. EE505.35 to 36 11
JK Flip-flop
•JK Flip-lop is the refinement of RS Flip-flop.
•JK Flip-flop has the features of SR and T flip-flops. Hence
it is known as ‘universal flip-flop’.
•The intermediate state (when R=S=1)of the RS type is
defined in the JK Flip-flop.

12. EE505.35 to 36 12
•when R=S=1 the state of output is changed i.e. the
complement of the previous state is available, i.e. Q
n+1= Q
n
•Q
n be the output (0 or 1) at a given time in the n
th
interval
(bit time n) preceding the n
th
clock pulse.
•Q
n+1is the corresponding output in the interval immediately
after the n
th
pulse.

13. EE505.35 to 36 13
JK Flip flop
Fig 5

14. EE505.35 to 36 14
The logic diagram of a clocked JK Flip-flop is
shown in the figure.

15. EE505.35 to 36 15
Truth table for JK flip-flop

16. EE505.35 to 36 16
Truth table for JK Flip flop

17. EE505.35 to 36 17
QUIZ
1. Name the flip-flop which has racing problem.
(a) RS flip-flop
(b) D flip-flop
(c) T flip-flop
(d) JK flip-flop

18. EE505.35 to 36 18
2.Universal Flip-Flop is
(a)RS flip-flop
(b)D flip-flop
(c)T flip-flop
(d)JK flip-flop

19. EE505.35 to 36 19
SUMMARY
We have discussed about
•RS Flip flop construction with NAND gates and Truth
table
•Refinement of RS Flip-flop as JK Flip-flop
•JK Flip-flop construction and Truthtable.

20. EE505.35 to 36 20
Frequently Asked Questions
1) Draw the schematic symbol and truth table of RS
flip-flop and explain.
2)Explain the operation of a clocked Rs flip-flop with
a neat timing diagram.
3)How JK flip-flop can be called as universal flip-flop.
4)Draw the logic diagram of a clocked JK flip-flop and
explain with truth table.