Tocci chapter 12 memory devices

Tocci chapter 12 memory devices

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Memory Devices

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Memory Terminology

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Memory Terminology

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1.Memory Cell: Bit
2.Memory Word: 8, 16, 32, 64, … etc
3.Byte: 8 bits.
4.Capacity: in Bytes
5.Density: Capacity
6.Address
7.Read: CPU reads
8.Write: CPU writes
9.Access time (t
ACC): between valid Memory: address, &
output.
Memory Terminology

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Memory Terminology
10.Volatile Memory: needs power
11.Random Access Memory (RAM): t
ACC≠�??????������.
12.Sequential Access Memory (SAM):t
ACC=�??????������.
13.Read/Write Memory (RWM)
14.Read Only Memory (ROM)
15.Static Memory: semiconductor, refreshment not required.
16.Dynamic Memory: semiconductor, requires refreshment.
17.Main Memory: high speed, semiconductor, stores active
instructions and data
18.Auxiliary Memory: external mass storage; HD, CD, DVD

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General Memory Operation

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Memory Technology

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CPU Memory Connections

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CPU Memory Connection

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Memory Types
SequentialRandom Access
SemiconductorMagnetic Optical
Volatile Nonvolatile
ROM RWM

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Memory Types
Random Access
Volatile Nonvolatile
Semiconductor
RWM
SRAM DRAMPROM EPROM EEPROM Flash-EEPROM
ROM

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Read Only Memories

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Typical ROM

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ROM Architecture

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Architecture of a 16 ×8 ROM

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ROM Timing

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Typical ROM Timing
Prepare Data
BJT: 30-90 nsCMOS:20-60 ns
Output Enable Time
BJT: 10-20 ns
CMOS:12-50 ns
Register
�??????????????????
Out Buffer
Out Buffer
�??????????????????
Data BusOutput Data

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Types of ROMs

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Types of ROM

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Mask-Programmed ROM Structure
4 Words
4 Bits/WordsA BitBit = 1
Bit = ?Bit = 0
2 Address Lines
A mask determines
where the metal is
deposited

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•For lower-volume applications, user-programmable fusible-link
PROMsare available; .
–Custom-programmed by the user, it cannot be erased and
reprogrammed.
One-Time Programmable
(OTP) ROMs.
Programmable ROM

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Erasable Non-Volatile Memory
1.EPROM
2.EEPROM
3.Flash
Same basic building block:
Floating Gate MOS
Erasable MOS

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Erasable MOS
1.Floating Gate
2.Charge Trapping
Erasable Non-Volatile Memory

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3 nm
Heavily Doped
Poly Silicon
Floating Gate MOS

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Floating Gate MOS

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Floating Gate MOS

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Floating Gate MOS
Simplified

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Floating Gate MOS
Actual
Oxide Thickness

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Floating Gate MOS
Bit selected by
memory decoder
Conducting
_ _ _ _ _
+ + + + +

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Floating Gate MOS
Bit Not selected by
memory decoder
Not conducting

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V
t1
Floating Gate MOS

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Programming Methods (0)
1.Fowler-Nordheim(FN) Tunneling
2.Channel Hot-Electron Injection (CHE)

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Fowler-Nordheim (FN) Tunneling
+ + + + + + + + + + +
+ + + + + + + + + + +
_ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _
_ _ _ _ _ _
_ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _

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+ + + + + + +
Fowler-Nordheim(FN) Tunneling
_ _ _ _ _ _ _ _

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+ +
Fowler-Nordheim(FN) Tunneling
_ _ _ _ _ _ _ _
+ + + + +

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Channel Hot-Electron Injection (CHE)

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Channel Hot-Electron Injection (CHE)

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Channel Hot-Electron Injection (CHE)
_
+ + + + + + + + + + +
+ + + + + + + + + + +
_ _ _ _ _ _ __ _ _ _ _ __ _ _ _ __ _ _ _``

39. Copyright Muhammad A M Islam.SBE202B Memory Devices 429/21/2020
Channel Hot-Electron Injection (CHE)
_
Hot Electrons
_
+ + + + + + + + + + +
+ + + + + + + + + + +
_ _ _ _ _ _ __ _ _ _ _ __ _ _ _ __ _ _ _``

40. Copyright Muhammad A M Islam.SBE202B Memory Devices 439/21/2020
Channel Hot-Electron Injection (CHE)
_ _
+ + + + + + + + + + +
+ + + + + + + + + + +
_ _ _ _ _ _ __ _ _ _ _ __ _ _ _ __ _ _ _``

41. Copyright Muhammad A M Islam.SBE202B Memory Devices 449/21/2020
Channel Hot-Electron Injection (CHE)
_
Avalanche Injection
_
_
+ + + + + + + + + + +
+ + + + + + + + + + +
_ _ _ _ _ _ __ _ _ _ _ __ _ _ _ __ _ _ _``
_ _ _ _ _ _ _ _
_ _ _ _ _ _ __ _ _ _ _ __ _ _ _

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Channel Hot-Electron Injection (CHE)
+ + + + + + +
_ _ _ _ _ _ _ _

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Floating Gate MOS Programming
________
+ + + + + + + +

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Floating Gate MOS Programming
________
+ + + + + + + +
Programming
Turns MOS off

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Floating Gate MOS Programming
V
t1 V
t0≈ 7 V

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Floating Gate MOS Programming
V
t1 V
t0
Sense Voltage

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Erasable Non-Volatile Memory
Structure: very close
1.EPROM: 1 MOS/Bit.
2.EEPROM: + An additional Access MOS/Bit.
3.Flash: Similar to EPROM.

48. Copyright Muhammad A M Islam.SBE202B Memory Devices 519/21/2020
Erasable Non-Volatile Memory
Programming: The Same
1.Tunneling.
2.Channel Hot-Electrons.

49. Copyright Muhammad A M Islam.SBE202B Memory Devices 529/21/2020
Erasable Non-Volatile Memory
Erasure:
1.EPROM: UV.
2.EEPROM: Similar to Programming. Individual words.
3.Flash: Similar to Programming. Bulk.

50. Copyright Muhammad A M Islam.SBE202B Memory Devices 539/21/2020
EPROM
First EPROM: 1967
1.OTP Cheap, Non-erasable.
2.UV Erasable 1000 times.

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EPROM Programming
1.Fowler-Nordheim(FN) Tunneling
2.Channel Hot-Electron Injection (CHE)

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UV Erasable EPROM
•Remove to programmor erase
•Erases all.
•1 Minute to load, & 20 to erase.
↑ UV → ↓ R
oxide→ Remove all Qs → all outputs = 1.
AUVlight is used
to clear the device.

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UV Erasable EPROM

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UV Erasable EPROM

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Similar to EPROM
Thinner Oxide
Electrically Erasable Programmable ROM (EEPROM)
EEPROM Structure1976

56. Copyright Muhammad A M Islam.SBE202B Memory Devices 619/21/2020
EEPROM Programming
Similar to EPROM
1.Fowler-Nordheim(FN) Tunneling
2.Channel Hot-Electron Injection (CHE)

57. Copyright Muhammad A M Islam.SBE202B Memory Devices 629/21/2020
_ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
+ + + + + + + +
+ + + + + + + +
+ + + + + + + +
+ + + + +
_ _ _ _ _ _ _
+ + + + + + + +
+ + + + + + + +
+ + + + +
+ + + + + + + +
Fowler-Nordheim(FN) Tunneling
EEPROM Erasure

58. Copyright Muhammad A M Islam.SBE202B Memory Devices 639/21/2020
+16 V
̶ 25 V
_ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
+ + + + + + + ++ + + + + + + +
+ + + + + +
+ + + +
+ +
+
+ + + + + + + +
+ + + + + + + +
+ + + + + + +
+ + + +
+ +
EEPROM Erasure
Drain Side Erasure

59. Copyright Muhammad A M Islam.SBE202B Memory Devices 659/21/2020
Solution:
1.extra circuitry to avoid excess discharging, and
2.Extra select MOS/bit
But!!!!!!!!!!!
If excess charge is removed
form the Floating Gate
EEPROM Erasure
_ _ _ _ _ _ _
+ + + + + + +
depletion MOS →on
while not selected

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EEPROM

61. Copyright Muhammad A M Islam.SBE202B Memory Devices 709/21/2020
EEPROM
A single EEPROM bit is made up
of two transistors: the MOS
transistor for erasure and the
floating gate transistor for storage

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EEPROM

63. Copyright Muhammad A M Islam.SBE202B Memory Devices 749/21/2020
CD ROM & DVD
1.Highly reflective surface.
2.Laser beam burns a point on the disk.
3.Data is stored as a continuous spiral.
4.A much less powerful laser beam for reading.

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Flash Memory

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Flash Memory
1980’s

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Flash Memory Storage

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Flash Memory Structure
Similar to EPROM
Thinner Oxide

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Flash Memory Storage
1.↑ density of EPROM & versatility of EEPROM.
2.Bulk Eraser: a block.
3.Dedicated hardware prevents over erasure.
4.One Select MOS per block.
5.Internal DC to DC converters → ↑ voltage.

69. Copyright Muhammad A M Islam.SBE202B Memory Devices 809/21/2020
28F256A CMOS Flash Memory
–Command codes →command register→:
•Chip operation.
•State control logic →logic and control signals.

70. Copyright Muhammad A M Islam.SBE202B Memory Devices 829/21/2020
Flash Memory Structure
Command Codes
•Read
•Erase
•E Verify
•Program
•Program Verify
Modern Flash
•V
PPis internally generated
•Burst Mode

71. Copyright Muhammad A M Islam.SBE202B Memory Devices 839/21/2020
Flash Memory Storage
NOR Flash
All Word
Lines are 0,
except for one
= 1
NAND Flash
All Word
Lines are
>V
HT, except
for one.
Faster
Block Erase
Block Erase

72. Copyright Muhammad A M Islam.SBE202B Memory Devices 849/21/2020
NORFlash Technology
•The first flash devices:
–Individual transistor Access.
•Offers: ↓??????
??????????????????& and random access.
•Application Ex: storing program instructions for
the mobile microcontroller.

73. Copyright Muhammad A M Islam.SBE202B Memory Devices 859/21/2020
NANDFlash Memory
•↑↑ Density.
–To access a transistor, the other word transistors,
having the same control gate voltage, are turned on
with �
��>�
��.

74. Copyright Muhammad A M Islam.SBE202B Memory Devices 869/21/2020
Flash Memory
•NAND: Data must be dealt with in blocks.
NANDflash is used for
mass storage of pictures,
music, and other files
in devices like digital
cameras, MP3 players
and USB flash drives.

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ROM Applications

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ROM Applications
Firmware:
•Automotive automatic braking systems, (ABS).
•Cell phones.
•Digital camcorder.
•Microwave ovens, etc.
Embedded microcontroller program memory:

77. Copyright Muhammad A M Islam.SBE202B Memory Devices 899/21/2020
ROM Applications
•Data transfer and portability:
–Cell phones
–Digital cameras.
–Flash drives.
–MP-3 players.

78. Copyright Muhammad A M Islam.SBE202B Memory Devices 909/21/2020
ROM Applications
•Bootstrap Memory:
–Contains a program that loads the operating system
programs from mass storage (disk) into a
computer’s main internal memory.

79. Copyright Muhammad A M Islam.SBE202B Memory Devices 919/21/2020
ROM Applications
•Data Table;e.g. : trigonometric functions
•Data Converter: e.g. BCD to LEDs’s7-segments.

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Function Generator

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Function Generator

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Semiconductor RAM

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Semiconductor RAM Types
•Architecture
•Types
–Static
–Dynamic

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RAM Architecture

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Internal Organization of a 64 ×4 RAM

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The Read Operation
WE orR/W = 1
????????????=??????
Input buffers are
disabled during
a data read.

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WE orR/W = 0
Tristate output
buffers are in
Hi-Z state during
a data write.
The Write Operation
????????????=??????

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Static RAM (SRAM)

89. Copyright Muhammad A M Islam.SBE202B Memory Devices 1019/21/2020
Static RAM (SRAM)
•Latches.
•BJT, MOS and BiCMOSvariations
–Majority CMOS.

90. Copyright Muhammad A M Islam.SBE202B Memory Devices 1029/21/2020
A CMOS SRAM Memory Cell
1
Off
Off
On
On
On
010 1
Off
0
Off On
OffOn
SC Latch
0
1
10
0
OnOff
1
Q = 0Q = 1

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READ Cycle Timing Diagram

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Write Cycle Timing Diagram

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Read-and write-cycle times of 12 ns.
–Standby power consumption of only 100 mW.
MCM6264C CMOS 8K x 8 RAM

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Static RAM (SRAM)
Standard Memory Packaging.

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Dynamic RAM (DRAM)

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DRAM Structure and Operation

97. Copyright Muhammad A M Islam.SBE202B Memory Devices 1099/21/2020
Dynamic RAM (DRAM)
•Stores data as charges on capacitors:
–Leakage.
–Periodical refreshment, typically every 2, 4, or 8 ms.
•↑↑capacities & ↓↓power consumption →the
memory of choice.

98. Copyright Muhammad A M Islam.SBE202B Memory Devices 1109/21/2020
DRAM Structure and Operation
Cell arrangement in a
16K x 1 dynamic RAM.
Total = 16,384 cells.

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Simplified Architecture Of A Typical DRAM

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During a WRITE operation, switches SW1 and SW2 are closed.
Symbolic Representation of DRAM Read and Write
Operations
During a aread operation, all switches are closed exceptSW1.

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DRAM Read/Write Cycles

102. Copyright Muhammad A M Islam.SBE202B Memory Devices 1149/21/2020
DRAM Read/Write
•Address Multiplexing.
•Row then column addresses.
•Address lines are connected to both the row &
column address registers.
–Upper part of the address
�??????�
row register.
–Lower part of the address
�??????�
column register.

103. Copyright Muhammad A M Islam.SBE202B Memory Devices 1159/21/2020
RAS Before CAS
DRAM Read/Write

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1XXXXXXXXXB
128 … 2550 … 127 128128
Simplified Architecture of DRAM
1K1K
0 255
0XXXXXXXXXB
CLK
CLK
4M ×1

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CPU Bus Driving Memory

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CPU Bus Driving Multiplexed Memory
1 10
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
Row
Address
Register
01
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7 A
6A
5A
4A
3A
2A
1A
0
Column
Address
Register
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8

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Timing of Address Multiplexing

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DRAM Read Cycle

109. Copyright Muhammad A M Islam.SBE202B Memory Devices 1219/21/2020
CPU Bus Driving Multiplexed Memory
1 10
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8

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DRAM Read Cycle

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CPU Bus Driving Multiplexed Memory
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
0 10
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
Row
Address
Register
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
1

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DRAM Read Cycle

113. Copyright Muhammad A M Islam.SBE202B Memory Devices 1259/21/2020
CPU Bus Driving Multiplexed Memory
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0 11
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8

114. Copyright Muhammad A M Islam.SBE202B Memory Devices 1269/21/2020
DRAM Read Cycle

115. Copyright Muhammad A M Islam.SBE202B Memory Devices 1279/21/2020
CPU Bus Driving Multiplexed Memory
0 01
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7
A6
A5
A4
A
3
A
2
A
1
A
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7 A
6A
5A
4A
3A
2A
1A
0 Column
Address
Register

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DRAM Read Cycle

117. Copyright Muhammad A M Islam.SBE202B Memory Devices 1299/21/2020
CPU Bus Driving Multiplexed Memory
0 01
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7
A6
A5
A4
A
3
A
2
A
1
A
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7 A
6A
5A
4A
3A
2A
1A
0
1

118. Copyright Muhammad A M Islam.SBE202B Memory Devices 1309/21/2020
DRAM Read Cycle

119. Copyright Muhammad A M Islam.SBE202B Memory Devices 1319/21/2020
CPU Bus Driving Multiplexed Memory
1 11
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7
A6
A5
A4
A
3
A
2
A
1
A
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7 A
6A
5A
4A
3A
2A
1A
0

120. Copyright Muhammad A M Islam.SBE202B Memory Devices 1329/21/2020
DRAM Write Cycle

121. Copyright Muhammad A M Islam.SBE202B Memory Devices 1339/21/2020
DRAM Write Cycle

122. Copyright Muhammad A M Islam.SBE202B Memory Devices 1349/21/2020
DRAM Write Cycle

123. Copyright Muhammad A M Islam.SBE202B Memory Devices 1359/21/2020
DRAM Write Cycle

124. Copyright Muhammad A M Islam.SBE202B Memory Devices 1369/21/2020
DRAM Write Cycle

125. Copyright Muhammad A M Islam.SBE202B Memory Devices 1379/21/2020
DRAM Write Cycle

126. Copyright Muhammad A M Islam.SBE202B Memory Devices 1389/21/2020
DRAM Write Cycle

127. Copyright Muhammad A M Islam.SBE202B Memory Devices 1399/21/2020
DRAM Write Cycle

128. Copyright Muhammad A M Islam.SBE202B Memory Devices 1409/21/2020
DRAM Refreshing
Not in Exam 31 May 2015

129. Copyright Muhammad A M Islam.SBE202B Memory Devices 1419/21/2020
DRAM Refreshing
Read → Entire Row Refreshment
Internal or External Refreshment Control Logic
Two Refreshment Modes:
1.Burst
2.Distributed
Every ≈ 4 ms! No guarantee

130. Copyright Muhammad A M Islam.SBE202B Memory Devices 1429/21/2020
DRAM Refreshing
Burst
1.Hold memory operation
2.Refresh all rows Sequentially
3.Refreshment counter for row address generation

131. Copyright Muhammad A M Islam.SBE202B Memory Devices 1439/21/2020
DRAM Refreshing
Distributed
1.Refreshment is interspersed with memory operation

132. Copyright Muhammad A M Islam.SBE202B Memory Devices 1449/21/2020
�??????�-Only Refresh
Most Universal
Strobe an internal row refresh counter with �??????�, while
????????????�and �??????remain HIGH.
A dynamic RAM (DRAM) controller is often used to perform
address multiplexing and refresh count sequence generation.
Refresh counter
Row Address
Hold Memory Operation
DRAM
Refresh entire rowStrobe

133. Copyright Muhammad A M Islam.SBE202B Memory Devices 1459/21/2020
DRAM Refreshing
Multiplex CPU and Refresh Counter Addresses
DRAM Controller
Dynamic DRAM Controller In PCs
1.Fully automatic: MUX Addresses, and control RAS
and CAS
2.Part of the chipset

134. Copyright Muhammad A M Islam.SBE202B Memory Devices 1469/21/2020
DRAM Refreshing
DRAMs today:
1.Have on-chip refreshment circuits
2.Needs only row addresses.

135. Copyright Muhammad A M Islam.SBE202B Memory Devices 1479/21/2020
CAS-before-RAS Refresh
1
2
Burst Refresh: n (�??????�–veedges) → n row refreshments
Refresh a rowIncrement internal address counter

136. Copyright Muhammad A M Islam.SBE202B Memory Devices 1489/21/2020
Burst ????????????�before �??????�Refresh
1 32
RAS before
CAS
2
Burst
``
Last

137. Copyright Muhammad A M Islam.SBE202B Memory Devices 1499/21/2020
Self Refresh
1
2
Fully Automatic
Refresh AllEvery 16 ms?

138. Copyright Muhammad A M Islam.SBE202B Memory Devices 1509/21/2020
DRAM Technology

139. Copyright Muhammad A M Islam.SBE202B Memory Devices 1519/21/2020
DRAM Modules
•SIMM(single in-line memory module): 72 functionally
equivalent contacts on both sides.
•DIMM (dual-in-line memory module): 168 to 240
functionally unique pins on each side.
•SODIMM(small-outline, dual-in-line memory module): for
compact applications, such as laptop computers.
•RIMM (Rambus In-line Memory Module): holds Direct
Rambus DRAM (DRDRAM).

140. Copyright Muhammad A M Islam.SBE202B Memory Devices 1529/21/2020
DRAM Technology
•FPM DRAM
•EDO DRAM
•SDRAM
•DDR SDRAM

141. Copyright Muhammad A M Islam.SBE202B Memory Devices 1539/21/2020
Fast Page Mode (FPM) DRAM
–Quick access within the current page.
–A Page has the same upper (row) address.
–Column address only needs to be updated

142. Copyright Muhammad A M Islam.SBE202B Memory Devices 1549/21/2020
Extended Data Output (EDO) DRAM
Within the same page:
1.Latch current memory to the output.
2.free CAS.
3.Prepare next Address while reading memory.

143. Copyright Muhammad A M Islam.SBE202B Memory Devices 1559/21/2020
Synchronous DRAM (SDRAM)
1.Successive memory locations are burst output.
2.First location is the slowest, due to address latching,
next addresses are clocked out.
3.Alternative access of banks (at least 2).
4.Self-refreshment.

144. Copyright Muhammad A M Islam.SBE202B Memory Devices 1569/21/2020
Double Data Rate (DDR) SDRAM
•Burst data at twice the speed of SDRAM.
•At both PGT & NGT.
•DDR2: 4X
•DDR3: 8X

145. Copyright Muhammad A M Islam.SBE202B Memory Devices 1589/21/2020
Magnetic Memory
Reels: of magnetic tape for long-term storage/retrieval
Hard Disk: coated with magnetic media and rotating
the disks while moving a magnetic read/write head
radially across the disk.

146. Copyright Muhammad A M Islam.SBE202B Memory Devices 1599/21/2020
•Magnetic Core: polarizable in either direction.
•The technology is revived recently in the form of
magneto-resistive random access memory (MRAM).
Magnetic Memory

147. Copyright Muhammad A M Islam.SBE202B Memory Devices 1609/21/2020
1.Compact Discs (CDs)
2.Digital video (DVD)
3.& Blu-Ray Discs (BD).
Essentially the same
technology, differing largely
in format & density.
Optical Memory

148. Copyright Muhammad A M Islam.SBE202B Memory Devices 1619/21/2020
Expanding Word Size and
Capacity

149. Copyright Muhammad A M Islam.SBE202B Memory Devices 1629/21/2020
Expanding Word Size
16×8

150. Copyright Muhammad A M Islam.SBE202B Memory Devices 1639/21/2020
Expanding Word Capacity
Build 1K ×8 using 1K ×1 ICs

151. Copyright Muhammad A M Islam.SBE202B Memory Devices 1649/21/2020
Expanding Word Capacity
Build 32 ×4 using 16 ×4 ICs

152. Copyright Muhammad A M Islam.SBE202B Memory Devices 1659/21/2020
Expanding Word Capacity
Inactive OutputsAddresses?
0
0
0
0
0 Build 8K ×8 using 2K ×8 ICs
CBA

153. Copyright Muhammad A M Islam.SBE202B Memory Devices 1669/21/2020
10
Expanding Word Capacity
Build 32K ×8 using 2K ×8 ICs
A
11
A
12
A
13
0
1
2
3
4
5
6
7
E
A
14
A
150
0
1
A
11
A
12
A
13
8
9
A
B
C
D
E
F
E
A
14
A
15
PROM
PROM
1

154. Copyright Muhammad A M Islam.SBE202B Memory Devices 1679/21/2020
Expanding Word Capacity
Addresses

155. Copyright Muhammad A M Islam.SBE202B Memory Devices 1689/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 00000
00000
1 00001
00001
2 00010
00010
3 00011
00011

156. Copyright Muhammad A M Islam.SBE202B Memory Devices 1699/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 0000000000000000
0000011111111111
1 00001
00001
2 00010
00010
3 00011
00011

157. Copyright Muhammad A M Islam.SBE202B Memory Devices 1709/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 0000000000000000 0000
0000011111111111 07FF
1 00001
00001
2 00010
00010
3 00011
00011

158. Copyright Muhammad A M Islam.SBE202B Memory Devices 1719/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 00000
00000
1 0000100000000000 0800
0000111111111111 0FFF
2 00010
00010
3 00011
00011

159. Copyright Muhammad A M Islam.SBE202B Memory Devices 1729/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 00000
00000
1 00001
00001
2 0001000000000000 1000
0001011111111111 17FF
3 00011
00011

160. Copyright Muhammad A M Islam.SBE202B Memory Devices 1739/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 00000
00000
1 00001
00001
2 00010
00010
3 0001100000000000 1800
0001111111111111 1FFF

161. Copyright Muhammad A M Islam.SBE202B Memory Devices 1749/21/2020
Expanding Word Capacity
Addresses
Prom Address Bus Hex
FEDCBA9876543210Address
0 0000000000000000 0000
0000011111111111 07FF
1 0000100000000000 0800
0000111111111111 0FFF
2 0001000000000000 1000
0001011111111111 17FF
3 0001100000000000 1800
0001111111111111 1FFF

162. Copyright Muhammad A M Islam.SBE202B Memory Devices 1759/21/2020
Incomplete Word Addressing
Car Dashboard: µP-Based
1.ROM for Program Storage.
2.RAM for meters: speed, RPM, Fuel, oil pressure,
engine temp, temp, battery voltage, … etc.
3.EEPROM for odometer (distance).
EEPROM Capacity < RAM

163. Copyright Muhammad A M Islam.SBE202B Memory Devices 1769/21/2020
Expanding Word Capacity
Incomplete address decoding is useful when different memory
devices are used in the same system
FEDCBA9876543210FEDCBA9876543210
000
PROM From To
0 0000 1FFF
FEDCBA9876543210
001
PROM From To
1 2000 3FFF
FEDCBA9876543210
010
PROM From To
2 4000 5FFF
FEDCBA9876543210
011-- 3
Aliasing
FEDCBA9876543210
01100
PROM From To
3 6000 67FF
FEDCBA9876543210
01101
PROM From To
3 6800 6FFF
FEDCBA9876543210
01110
PROM From To
3 7000 77FF
FEDCBA9876543210
01111
PROM From To
3 7800 7FFF

164. Copyright Muhammad A M Islam.SBE202B Memory Devices 1779/21/2020
Expanding Word Capacity

165. Copyright Muhammad A M Islam.SBE202B Memory Devices 1789/21/2020
Combining DRAM Chips
1.Word size is often 1 or 4 bits
2.Address is always multiplexed; RAS, and CAS.
3.On-chip DRAM Refresh Control Circuit.

166. Copyright Muhammad A M Islam.SBE202B Memory Devices 1799/21/2020
Combining DRAM Chips
Build 4M ×8 using 4M ×1 ICsDRAM ICs with word sizes of 1-4 bits must be
combined to form larger word size modules

167. Copyright Muhammad A M Islam.SBE202B Memory Devices 1809/21/2020
Special Memory Functions

168. Copyright Muhammad A M Islam.SBE202B Memory Devices 1819/21/2020
Special Memory Functions
1.Power-Down Storage
2.Cache Memory
3.First-In First-Out Memory (FIFO)
4.Circular Buffers

169. Copyright Muhammad A M Islam.SBE202B Memory Devices 1829/21/2020
Power-Down Storage
Storage of critical Data.
Examples:
1.Printers: # of copies.
2.Industrial Process Control Systems

170. Copyright Muhammad A M Islam.SBE202B Memory Devices 1839/21/2020
Power-Down Storage
Critical Data Storage Approaches:
1.Low Power RAM with backup batteries (implanted!): Drainage.
2.Flash: Entire memory must be rewritten.
3.When power is down, move data form RAM to battery operated
RAM or Flash. When power is back, return data.

171. Copyright Muhammad A M Islam.SBE202B Memory Devices 1869/21/2020
Cache Memory
Extremely High Speed RAM.
1.CPU Cache: In the CPU or next to it on a separate chip.
Runs at the CPU Clock not BUS clock.
2.Hard Disk Cash:
CPU
L1
Chipset
L2
Mother Board
RAM

172. Copyright Muhammad A M Islam.SBE202B Memory Devices 1909/21/2020
First-In-First-Out Memory (FIFO)
Linear Buffer
Data-Rate-Buffer: for communication between systems
with different data transfer rates.
Operation is controlled by address pointer registers.
1
2
3
4
5
6
7
8
In
Out
D
1D
2D
3D
4D
5D
6D
7D
8

173. Copyright Muhammad A M Islam.SBE202B Memory Devices 1929/21/2020
Circular Buffers
Stores the last entered n values.

174. Copyright Muhammad A M Islam.SBE202B Memory Devices 1939/21/2020
Circular Buffers
1
2
3
n
n-1
4
D
1
D
2
D
3
D
3
D
n-1
D
n
D
n+1
D
n+1
D
n+1
D
n+1
Stores the last entered n values.