UNIT-3.pptx digital electronics system 34

Microprocessor memory management for Intel 80386 microprocessor.Its details and it's structure.Its diagram and it's discription.

1. UNIT-3 Memory Management

2. Segmentation  8086 microprocessor has memory size is  1MB. Thus we use a 20-bit physical address (actual address) to satisfy 1MB memory with unique addresses . The unique address of every memory location is called a physical address. Every memory location should have a unique address. The physical address is 20 bit, and it is not a  byte compatible   number. Segmentation  involves logically dividing the computer’s main memory into distinct segments, each with its own base address. 8086 is divided into 4 segments i.e.  Code, Stack, Data and Extra segment and each segment is 64 KB in size. Program is stored sequentially in Code segment.Variables or data stored sequentially in Data and Extra segment . The stack segment will be stored in the last in first out order (Return Addresses)

3. Segment Register Segment Register Designated Role CS Code Segment Register This register points to the currently active code segment. Used in conjunction with the IP register to point to the next instruction to be fetched and executed by the processor. DS Data Segment Register This register usually points to the default data segment which contains the global and static variables of the active application. ES Extra Segment Register General purpose segment register used mostly for data transfers between different segments. SS Stack Segment Register This register points to the segment containing the active stack. The top of stack is located at address SS:SP.

4. Memory Management(8086) Virtual Address(Logical Address): If you have a 20-bit address bus then you are bound to have a 20-bit address but 20 bit is not byte compatible. To solve this we use16-bit address which is named virtual address so that we don’t have to use a physical address. The virtual address is a combination of segment address and offsets address. The segment address shows the segment you want to access. Offset address is the distance from the starting of a segment to the location you want to access . Physical Address:-   The combination of a segment and an offset within that segment forms a physical address.

5. Real-Mode Memory Management(8086) PHYSICAL ADDRESS = SEGMENT ADDRESS X 10H + OFFSET ADDRESS

6. Memory Management in 80386

7. Segmentation:-Logical address to Physical Address In Segmentation Logical address of 48 bit is converted into 32 linear address.

8. Selector(16bit) Content of Segment Register(CS ,DS,SS,ES ) is used as Selector Selector Selects one of the 8192 Descriptor from one of the table i.e GDT and LDT . Descriptor Index and Table Index (TI)  : The 13 bit descriptor index selects one of up to 8K descriptors in either the GDT and LDT, as specified by the TI bit. Therefore, these 14 bits allows access to 16K 8-byte descriptors. RPL  : The desired privilege level of the program. Access is granted if the RPL value is lower (higher in privilege) than the AR of the segment. Otherwise, a privilege violation is issued

9. Segmentation provides both memory management and protection . All information about the segments is stored in an 8-byte data structure called a descriptor . All the descriptors are stored in tables identified by the 80386 hardware. There are three types of tables holding 80386 descriptors: global descriptor table (GDT ) local descriptor table ( LDT) interrupt descriptor table (I DT ). 80386 processor have many LDT but only one GDT and one IDT.

10. BASE: It contains the 32-bit base address for a segment. Thus define the location of the segment within the 4 gigabyte Physical Memory. LIMIT: It defines the size of the segment.    When the processor concatenates the two parts of the limit field, a 20-bit value results. The processor interprets the limit field in one of two ways, depending on the setting of the granularity bit:

11. 80386 Descriptor segment descriptors are a part of the segmentation unit, which provides the processor with the data it needs to translate a logical address into a linear address. A(Accessed bit):- This bit indicate whether segment has been accessed by CPU or not. Type field(4 bits)- This field decide the descriptor Type and Segment Type. S Bit:- This bit decide whether it is a(S=0) system descriptor or (S=1) Segment descriptor(Code /Data Segment ). DPL( descriptor Privilege level ):- This field decide descriptor Privilege level. D bit:-D bit specify the code segment operation Size. If D=1 segment is 32 bit operand segment else 16 bit operand segment. P bit:- P bit specify whether segment is present in Physical memory or not. G (Granularity )bit:-This bit indicate whether segment is Page addressable. AVL(U Bit):- This field specify whether the descriptor is available to user or to the operating system. Zero bit must remain Zero for Compatibility with future processor.

12. GDTR is the GDT (Global Descriptor Table) Register. It contains the base address (linear) and limit for the GDT, and is set using lgdt . LDTR is the LDT (Local Descriptor Table) Register and contains the linear base address and limit for the LDT.

13. LDTR is a 16 bit Register used to point LDT Descriptor.

14. GDT( Global Descriptor Table ) GDT is Global Descriptor Table.GDT Represent the global memory area shared by all tasks. There are total 8192 descriptors in GDT. Each Descriptor is of 64KB size.(8 Bytes)

15. Paging unit enabled in protected mode

16. Paging Mechanism

17. Control Register 3 (CR3) :- Control register 3 holds the physical address of the root of the two level paging tables used when paging is enabled. It is also called Page Directory Base Register .

18. Page Descriptor Base Register  The 32-bit linear address is stored at the control register CR2 at which the previous page fault can be detected. The control register CR3 is used as page directory which is known as physical base address register. Hence, CR3 is used to store the physical starting address of the page directory. The lower 12 bits of CR3 must be zero so that page size must be 4K and the page size must be aligned with the directory. Page Directory  The size of the page directory is 4 Kbytes. Each directory entry consists of four bytes. Consequently, a total of 1K or 1024 entries are allowed in a directory. The example of a typical directory entry is shown in Fig. 11.42. The upper 10 bits of the linear address are used as an index to the equivalent page directory entry. The corresponding page directory entry is used to indicate the page tables.

19. P-bit  The P-bit can be used in address translation. When P = 1, the entry can be used in address translation. If P = 0, the entry cannot be used. The P-bit of the presently executed page is always high. U/S and R/W Bit  The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide the four level protections as shown in Table 11.21. The level 0 has the highest privilege level, but the level 3 has the lowest privilege level. A-bit  The A-bit (access bit) must be set by the 80386 processor before accessing any page. If A = 1, the page is accessed. When A=0, the page is not accessed. D-bit  The D-bit (Dirty bit) is set before a write operation to the page. The D-bit is undefined for page directory entries. The OS reserved bits are defined by the operating system

20. Types of system and non - system descriptors

21. System descriptors :- 1 . A Local Descriptor Table descriptors (LDT):- S bit is’0’ and type bit ‘2’. LDTR selects the LDT Descriptor from Global Descriptor Table. They points to the base of LDT. Each task has its own Local Descriptor, which is not shared by other tasks. LDT can be accessed by user if its privilege level is 0.Otherwise DPL level is neglected.

22. 2. Task State Segment(TSS):-

23. A Gate Descriptor is special type of Descriptor . The 80386 uses this Gate Descriptor for performing protection Check. There are four types Gate Descriptor: Call Gate :-(Type=4) Call Gate used to call functions which is at another privilege level .It can Change the privilege level and transfer program control to higher privilege level. Interrupt Gate:- :- ( Type=6) IDTR used to select the descriptor from GDT .This selected descriptor is called as Interrupt Gate. Interrupt Gate points to corresponding ISR(Interrupt service routine) to be executed. Task Gate:- :- (Type=5) They are used in multitasking systems to perform task switching.The task register selects the task gate similar to LDTR selecting LDT descriptor. Task gate then selects the Task state Segments(TSS)that is used to copy the content of Current task. On return from this Task ,the content of TSS is again loaded into registers.  Trap Gate :-(Type=7) Trap gate is used to handle the single stepping interrupt .

24. The segmentation can divide the physical memory into different sizes of segments while the Paging divides the memory into fixed-size pages of 4KB. The main advantage of the paging system is that it is not required in the complete segment of a task in the physical memory at any time. But only some required pages of the segments should he available in the physical memory for the execution. When the remaining pages of the specified task are required for execution, these pages can be fetched from the secondary memory storage devices.

25. Combining Segment and Page Translation