Unit 3 - Styles of Modeling-1 for resource management techniques

Styles of modelling in resource management techniques

1. ONLINE CLASS
PROGRAMMING IN HDL (SEC1406)
MENTORS
Dr.T.RAVI
Dr.T.VINO
Department of ECE
Sathyabama Institute of Science and Technology

2. SYLLABUS

3. Course Outcome
After the completion of course student will be able to
CO1Understand the requirements of VHDL design flow
CO2Interpret the Veriloglanguage elements and its relevance to
digital design
CO3Apply the ModellingStyles for Simulation, Synthesis and
Test Bench Creation.
CO4Analysethe Performance Study of Combinational and
Sequential logic design using Verilog
CO5Evaluate State Machine and Memory designs by Verilog
CO6Create and realize the system in FPGA using Verilog

4. UNIT 3
STYLES OF MODELING IN VERILOG HDL

5. GATE LEVEL MODELING
Built-in Primitive gates in Verilog HDL
•Multiple input gates:
and, nand, or, nor, xor, xnor
•Multiple output gates:
buf, not
•Tristate Gates:
bufif0, bufif1, notif0, notif1
•Pull gates:
pullup, pulldown
•Mos switches:
cmos, nmos, pmos, rcmos, rnmos, rpoms
•Bidirectional switches:
tran, tranif0, tranif1, rtran, rtranif0, rtranif1

6. Multiple-input Gates
Multiple input gates (One output and variable number of inputs)
nand (y, in1, in2) ;
nand (y, in1, in2, in3) ;
nand (y, in1, in2, in3, in4) ;
First terminal is output, followed by inputs
and a1 (out1, in1, in2);
nanda2 (out2, in21, in22, in23, in24);
and, nand, or, nor, xor, xnor

7. Multiple-output Gates
not andbuf
variable number of outputs but only one input
One or more outputs first, followed by one input
not N1 (OUT1, OUT2, OUT3, OUT4, INA);
bufB1 (BO1, BIN);

8. Tristate Gates
bufif0, bufif1, notif0, notif1
Output terminal first, then input, then control
bufif1 BF1 (OUTA,INA,CTRLA);

9. Pull Gates
pullup, pulldown
These gates have only one output with no inputs.
Pullup gate places a 1 on its output.
Pulldown gate places a 0 on its output.
PullupPUP (Pwr);
oPullup gate has instance name PUP with output Pwrtied to 1.
pullup PUP (PwrA, PwrB, PwrC);

10. MOS Switches
cmos, nmos, pmos, rcmos, rnmos, rpoms
ctl
in out nmos(out, in,ctl);
nMOS(unidirectional)
ctl
in out pmos(out, in,ctl);pMOS(unidirectional)
pctl
nctl
outcmos(out, in, nctl,pctl);
cMOS (unidirectional)in
r-resistive gate type [name] (output, input, control input)
nmos n1 (z, a, c),
cmos [name] ( output, input, Ncontrol1, pcontrol1)

11. tran, tranif0, tranif1, rtran, rtranif0, rtranif1
tran[instance name] (signalA, signalB);
Gatetype [instance name] (signala, signalb, control);
Bidirectional Switches

12. User DefinedPrimitives
UDPs permittheusertoaugment thesetofpre-
defined primitive elements.
UDP is instantiated exactly the same way as a primitive gate
(ie. it is identical to a gate instantiation).
Use of UDPs may reduce the amount of memory required for simulation.
Both Combinational and sequential (level-sensitive and edge-sensitive
behavior) is supported.

13. UDP TableSymbols
symbol Interpretation Comments
0 Logic 0
1 Logic 1
x Unknown
? Iteration of 0, 1, and x input field
b Iterayion of 0 and 1 input field
- No change output field
(vw) Change of value from v to w
* Same as (??) Any value change on input
r Same as (01) Rising edge on input
f Same as (10) Falling edge on input
p Iteration of (01), (0x), and (x1)Positive edge including x
n Iteration of (10), (1x), and (x0)Negative edge including x

14. Combinational UDP
// 2X1 mux
primitivemux2X1(o,a,b,s);
output o;
input a,b,s;
table
// a b s : o
0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
0 0 x : 0;
1 1 x : 1;
endtable
endprimitive
Theoutputportmustbethefirstport.
UDPdefinitionsoccuroutsideofamodule
AllUDPportsmustbedeclaredasscalar
inputsoroutputs.UDPportscannotbe
inout.
Tablecolumnsareinputsinorder
declaredinprimitivestatement-colon,
output, followed by a semicolon.
Anycombinationofinputswhichisnot
specifiedinthetablewillproducean'x'at
theoutput.

15. 4X1mux built using 2X1mux UDPs
module mux4X1(Z, A, B, C, D, sel);
input A, B, C, D;
input [2:1] sel;
output Z;
mux2X1
(TL, A, B, Sel[1]),
(TP, C, D, Sel[1]),
(Z, TL, TP, Sel[2]);
endmodule
Combinational UDP (conti….)

16. Sequential UDP
Initial state is described using a 1-bit register.
The value of this register is the output of sequential UDP.
There are two different kinds of sequential UDP
level sensitiveand edge-sensitive behavior
•The current value of the register and the input values to
determine the next value (output) of the register.

17. Level-sensitive Sequential UDP
primitivelatch(q,clock,data);
output q;
reg q;
input clock,data;
table
// clock data : state_output :next_state
1:
0:
?:
?
?
?
:
:
:
1;
0;
-;
0
0
1
endtable
endprimitive
The'?'isusedtorepresentdon't
careconditionineitherinputsor
currentstate.
The'-'intheoutputfieldindicates
'nochange'.

18. Edge-triggered Sequential UDP
primitived_edge_ff(q,clock,data);
output q; // ignore negative edge of clock
reg q;
input clock, data;// ignore data changes on steady clock
table
// obtain output on rising edge of clock
// clock data state next
(01)0 :?:0;
(01)1 :?:1;
(0x)1 :1:1;
(0x)0 :0:0;
endtable
endprimitive
Notethatthetablenowhasedgeterms
representingtransitionsoninputs.

19. •Write an UDP for 3-bit majority circuit.
(output is 1 if the input vector has two or more 1’s)
User DefinedPrimitives

20. •Write an UDP for 3-bit majority circuit.
(output is 1 if the input vector has two or more 1’s)
User DefinedPrimitives
primitive majority3 (Z, A, B, C);
input A, B, C;
output z;
table
// A B C : Z
0 0 ? : 0;
0 ? 0 : 0;
? 0 0 : 0;
1 1 ? : 1;
1 ? 1 : 1;
? 1 1 : 1;
endtable
endprimitive

21. STYLES OF MODELING IN VERILOG HDL
Different Styles of Modeling
–Data flow Modeling
–Structural Modeling
–Behavioral Modeling
–Mixed Modeling

22. Uses continuous assignment statement (Concurrent Statements)
Format: assign[ delay ] net = expression;
Example: assignsum = a ^ b;
Delay: Time duration between assignment from RHS to LHS
All continuous assignment statements execute concurrently
Order of the statement does not impact the design
Dataflow Modeling
// Full adder Data flow Modeling
modulefulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign sum = a^b^c;
assign #2 carry = (a & b) | (b & c) | (c & a);
endmodule

23. The target in a continuous assignment is one of the following:
Scalar net (assignsum = a ^ b;)
Vector net (wire [3:0]z; assign z = ….. )
Constant bit-select of a vector (assign z[1]=…)
Constant part-select of a vector (assign z[1:2]=…)
Concatenation of any of the above
wire cout, cin;
wire [3:0]sum, a, b;
….
assign {cout, sum}= a+b+cin;
Dataflow Modeling

24. Delay can be introduced
Example: assign#2 sum = a ^ b;
“#2” indicates 2 time-units
No delay specified : 0 (default)
Associate time-unit with physical time
`timescale time-unit/time-precision
Example: `timescale1ns/100 ps
Timescale
`timescale1ns/100ps
1 Time unit = 1 ns
Time precision is 100ps (0.1 ns)
10.512ns is interpreted as 10.5ns
Dataflow Modeling
Delays (Cont….)

25. Example:
`timescale1ns/100ps
moduleHalfAdder(A, B, Sum, Carry);
inputA, B;
outputSum, Carry;
assign#3 Sum = A ^ B;
assign#6 Carry = A & B;
endmodule
Dataflow Modeling
Delays (Cont….)

26. // Full adder Data flow –VerilogHDL
modulefulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign sum = a^b^c;
assign carry = (a & b) | (b & c) | (c & a);
endmodule
// Full adder -VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_dataflowis
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_dataflow;
architecture dataflow of fadd_dataflowis
signal p,q,r:std_logic;
begin
p<= a and b;
q<= b and c;
r<= c and a;
sum<= ((a xorb) xorc);
carry<= p or q or r;
end dataflow;
Data flow Modeling in
Verilog HDL & VHDL
(Ex:Full Adder)
p
q
r
x1
a1
a2
a3
o1p
q
r

27. Full subtractor-Dataflow Modeling
ABCDIFFERENCE BORROW
000 0 0
001 1 1
010 1 1
011 0 1
100 1 0
101 0 0
110 0 0
111 1 1
modulefulsubdataflow(a, b, cin, diff, borrow);
input a;
input b;
input cin;
output diff;
output borrow;
wire abar;
assign abar= ~ a;
assign diff=a^b^cin;
assign borrow=(abar& b) | (b & cin) |(cin& abar);
endmodule

28. moduleencod_data(D, X, Y,Z);
input [7:0] D;
output X;
output Y;
output Z;
assign #3 X=D[4] | D[5] | D[6] | D[7];
assign #3 Y=D[2] | D[3] | D[6] | D[7];
assign #3 Z=D[1] | D[3] | D[5] | D[7];
endmodule
8 X 3 Encoder -Dataflow Modeling
D0D1D2D3D4D5D6D7XYZ
10000000000
01000000001
00100000010
00010000011
00001000100
00000100101
00000010110
00000001111

29. moduledecoderdataflow(a,b,en, z);
input a,b,en;
output [0:3] z;
wire abar,bbar;
assign # 1 abar=~a;
assign # 1 bbar=~b;
assign # 2 z[0]=~ (abar& bbar& en);
assign # 2 z[1]=~ (abar& b & en);
assign # 2 z[2]=~ (a & bbar& en);
assign # 2 z[0]=~ (a & b & en);
endmodule
2 x 4 Decoder -Dataflow Modeling
AB EZ(0)Z(1)Z(2)Z(3)
00 1 0 1 1 1
01 1 1 0 1 1
10 1 1 1 0 1
11 1 1 1 1 0

30. modulemuxdataflow (s, i, y);
input [1:0] s;
input [3:0] i;
output y;
wire s2,s3,s4,s5,s6,s7;
assign s2 = ~s[1];
assign s3 = ~s[0];
assign s4 = i[0] & s2 & s3;
assign s5 = i[1] & s2 & s[0];
assign s6 = i[2] & s[1] & s3;
assign s7 = i[3] & s[1] & s[0];
assign y = s4 | s5 | s6 | s7;
endmodule
4 X 1 Multiplexer -Dataflow Modeling
SELECT INPUT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

31. moduledemuxdataflow (s0,s1,i,y);
input s0,s1,i;
output [3:0] y;
wire s2,s3;
assign #2 s2=~s0;
assign #2 s3=~s1;
assign #3 y[0]=I & s2 & s3;
assign #3 y[1]=I & s2 & s1;
assign #3 y[2]=I & s0 & s3;
assign #3 y[3]=I & s0 & s1;
endmodule
1 X 4 Demultiplexer -Dataflow Modeling
INPUT OUTPUT
D S0S1Y0Y1Y2Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

32. Structural Modeling

33. // Full adder –VerilogHDL
modulefulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire p,q,r,s;
xor
x1(p,a,b),
x2(sum,p,c);
and
a1(q,a,b),
a2(r,b,c),
a3(s,a,c);
or
o1(carry,q,r,s);
endmodule
Structural Modeling in
VerilogHDL & VHDL
(Ex:FullAdder)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_structuralis
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_structural;
architecture structural of fadd_structuralis
component xor2
port(a,b:instd_logic;
z:out std_logic);
end component;
component and2
port(a,b:instd_logic;
z:out std_logic);
end component;
component or3
port(a,b,c:instd_logic;
z:out std_logic);
end component;
signal p,q,r,s:std_logic;
begin
x1: xor2 port map (a,b,p);
x2: xor2 port map (p,c,sum);
a1: and2 port map (a,b,q);
a2: and2 port map (b,c,r);
a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;

34. Structural: Logic is described in terms of Verilog gate primitives
module eg1 (a,b,c,f);
input a,b,c;
output f;
wire g,h,i;
and(g,a,b);
not(h,b);
and(i,h,c);
or (f,g,i);
endmodule
Gate LevelModeling
a
c
F = AB +B'C
b
f
g
ih

35. Full subtractor-Structural Modeling
ABCDIFFERENCE BORROW
000 0 0
001 1 1
010 1 1
011 0 1
100 1 0
101 0 0
110 0 0
111 1 1
modulefs_struct(a, b, c, diff, borrow);
input a;
input b;
input c;
output diff;
output borrow;
wire abar,p,q,r,s;
not
n1(abar,a);
xor
x1(p,a,b),
x2(diff,p,c);
and
a1(q,abar,b),
a2(r,b,c),
a3(s,abar,c);
or
o1(borrow,q,r,s);
endmodule

36. moduleencod_struct(D, X, Y,Z);
input [7:0] D;
output X;
output Y;
output Z;
or
o1(x,d[4],d[5],d[6],d[7]),
o2(y,d[2],d[3],d[6],d[7]),
o3(z,d[1],d[3],d[5],d[7]);
endmodule
8 X 3 Encoder -Structural Modeling
D0D1D2D3D4D5D6D7XYZ
10000000000
01000000001
00100000010
00010000011
00001000100
00000100101
00000010110
00000001111

37. moduledecoder_structural (a,b,e, z);
input a,b,e;
output [0:3] z;
wire abar,bbar;
not
n1(abar,a),
n2(bbar,b);
nand
a1(z[0],abar,bbar,e),
a2(z[1],abar,b,e),
a3(z[2],a,bbar,e),
a4(z[3],a,b,e);
endmodule
2 x 4 Decoder -Structural Modeling
AB EZ(0)Z(1)Z(2)Z(3)
00 1 0 1 1 1
01 1 1 0 1 1
10 1 1 1 0 1
11 1 1 1 1 0

38. modulemux_structural (a,b, i, y);
input a,b;
input [3:0] i;
output y;
wire s1,s2,s3,s4,s5,s6;
not
n1(s1,a),
n2(s2,b);
and
a1(s3,i[0],s1,s2),
a2(s4,i[1],s1,b),
a3(s5,i[2],a,s2),
a4(s6,i[3],a,b);
or
o1(y,s3,s4,s5,s6);
endmodule
4 X 1 Multiplexer -Structural Modeling
SELECT INPUT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

39. moduledemux_structural (s0,s1,i,y);
input s0,s1,i;
output [3:0] y;
wire s2,s3;
not
n1(s2,s0),
n2(s3,s1);
and
a1(y[0],i,s2,s3),
a2(y[1],i,s2,s1),
a3(y[2],i,s0,s3),
a4(y[3],i,s0,s1);
endmodule
1 X 4 Demultiplexer -Structural Modeling
INPUT OUTPUT
D S0S1Y0Y1Y2Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

40. Ripple Carry Adder (RCA)-Structural Modeling
modulerca_structural(a, b, c, s, cout);
input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output cout;
wire c1,c2,c3;
fulladddataflow
f1(a[0],b[0],c,s[0],c1),
f2(a[1],b[1],c1,s[1],c2),
f3(a[2],b[2],c2,s[2],c3),
f4(a[3],b[3],c3,s[3],cout);
endmodule
modulefulladddataflow(a, b, cin, sum, carry);
input a;
input b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=(a & b) | (b & cin) | (cin & a);
endmodule

41. Example:
module mux_2x1(a, b, sel, out);
inputa, b, sel;
outputout;
Reg out;
always@(a orb orsel)
begin
if(sel== 1)
out = a;
elseout = b;
end
endmodule
Behavioral Modeling

42. Two Procedural Constructs
initialStatement
alwaysStatement
initialStatement : Executes only once
alwaysStatement : Executes in a loop
Example:
…
initial begin
Sum = 0;
Carry = 0;
end
…
…
always@(A or B) begin
Sum = A ^ B;
Carry = A & B;
end
…
Procedural Constructs

43. Initial Statement
initial
[timing _control] procedural_statement
Where, a procedural statement is one of:
Procedural_assignment
Procedural continoues_assignment
conditional_statement
case_statement
loop_statement
wait_statement
…..

44. alwaysstatement : Sequential Block
Sequential Block: All statements within the block are executed sequentially
When is it executed?
Occurrence of an event in the sensitivity list
Event: Change in the logical value
Statements with a Sequential Block: Procedural Assignments
Procedural Assignments may optionally have a delay
Inter-Statement Delay
Intra-Statement Delay
Behavioral Modeling (Cont…)

45. Inter-Assignment Delay
Example:
Sum = A ^B;
#2 Carry = A &B;
Delayed execution
Intra-Assignment Delay
Example:
Sum = A ^ B;
Carry = #2 A & B;
Delayed assignment
Behavioral Modeling (Cont…)

46. // Full adder Data flow Modeling
modulefulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire p,q,r;
assign p = a & b;
assign q = b & c;
assign r = a & c;
assign sum = (a^b)^c;
assign carry = p | q | r;
endmodule
Modeling in Verilog HDL (Ex:Full Adder)
// Full adder Structural Modeling
modulefulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire p,q,r;
xor
x1(sum,a,b,c);
and
a1(p,a,b),
a2(q,b,c),
a3(r,a,c);
or
o1(carry,p,q,r);
endmodule
// Full adder Behavioral Modeling
module fulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
regsum,carry;
reg p,q,r;
always @ (a or b or c)
begin
sum = (a^b)^c;
p=a & b;
q=b & c;
r=a & c;
carry=(p | q) | r;
end
endmodule
p
r
x1
a1
a3
o1p
r

47. Behavioral Modeling in
Verilog HDL & VHDL
(Ex:Full Adder)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_behvis
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_behv;
architecture Behavioral of fadd_behvis
begin
process(a,b,c)
variable p,q,r:std_logic;
begin
p:= a and b;
q:= b and c;
r:= c and a;
sum<= a xorb xorc;
carry<= p or q or r;
end process;
end Behavioral;
// Full adder Behavioral Modeling
module fulladd(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
regsum,carry;
reg p,q,r;
always @ (a or b or c) begin
sum = (a^b)^c;
p=a & b;
q=b & c;
r=a & c;
carry=(p | q) | r;
end
endmodule

48. moduleencoder_behav(d, x, y, z);
input [7:0] d;
output x;
output y;
output z;
reg x,y,z;
always @ (d [7:0])
begin
x= d[4] | d[5] | d[6] | d[7];
y= d[2] | d[3] | d[6] | d[7];
z= d[1] | d[3] | d[5] | d[7];
end
endmodule
8 X 3 Encoder -BehavioralModeling
D0D1D2D3D4D5D6D7XYZ
10000000000
01000000001
00100000010
00010000011
00001000100
00000100101
00000010110
00000001111

49. moduledecoderbehv(a, b, e, z);
input a;
input b;
input e;
output [3:0] z;
reg [3:0] z;
always @ (a,b,e)
begin
z[0] = ~ ((~a) & (~b) & e);
z[1] = ~ ((~a) & b & e);
z[2] = ~ (a & (~b) & e);
z[3] = ~ (a & b & e);
end
endmodule
2 x 4 Decoder -Behavioral Modeling
AB EZ(0)Z(1)Z(2)Z(3)
00 1 0 1 1 1
01 1 1 0 1 1
10 1 1 1 0 1
11 1 1 1 1 0

50. moduledemux_behv(s0, s1, Din, y);
input s0;
input s1;
input Din;
output [3:0] y;
reg [3:0] y;
reg s2,s3;
always@(Din or s0 or s1)
begin
s2=~s0;
s3=~s1;
y[0]=Din & s2 & s3;
y[1]=Din & s2 & s1;
y[2]=Din & s0 & s3;
y[3]=Din & s0 & s1;
end
endmodule
1 X 4 Demultiplexer -BehavioralModeling
INPUT OUTPUT
D S0S1Y0Y1Y2Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

51. Event Control
Edge Triggered Event Control
Level Triggered Event Control
Edge Triggered Event Control
@(posedgeCLK) //Positive Edge of CLK
Curr_State= Next_state;
Level Triggered Event Control
@(A orB) //change in values of A or B
Out = A & B;
Event Control

52. Loop Statements
Loop Statements
Repeat
While
For
Repeat Loop
Example:
repeat(Count)
sum = sum + 5;
If condition is a xor zit is treated as 0

53. 53
Loop Statements (cont.)
While Loop
Example:
while(Count < 10) begin
sum = sum + 5;
Count = Count +1;
end
If condition is a xor zit is treated as 0
For Loop
Example:
for(Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5;
end

54. 54
Conditional Statements
ifStatement
Format:
if(condition)
procedural_statement
else if(condition)
procedural_statement
else
procedural_statement
Example:
if(Clk)
Q = 0;
else
Q = D;

55. moduledff(d,clk,rst,q,qbar);
inputd;
inputclk;
inputrst;
outputq;
outputqbar;
regq;
regqbar;
always@(posedge(clk)orposedge(rst))
begin
if(rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
elseif(d==1'b0)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=1'b1;
qbar=1'b0;
end
end
endmodule
D FF–using if statement
Q(t) D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

56. 56
Conditional Statements (cont.)
Case Statement
Example 1:
case(X)
2’b00: Y = A + B;
2’b01: Y = A –B;
2’b10: Y = A / B;
endcase
Example 2:
case(3’b101 << 2)
3’b100: A = B + C;
4’b0100: A = B –C;
5’b10100: A = B / C; //This statement is executed
endcase

57. modulemux_behv(D, s0, s1, y);
input [3:0] D;
input s0;
input s1;
output y;
reg y;
always@(D or s0 or s1)
begin
case({s1,s0})
2'd0:y=D[0];
2'd1:y=D[1];
2'd2:y=D[2];
2'd3:y=D[3];
default:$display("invalid control signals");
endcase
end
endmodule
4 X 1 Multiplexer –using case statement
SELECT INPUT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

58. SR Flip Flop

59. JK Flip Flop

60. T Flip Flop

61. SISO Shift Register
modulesiso(din,clk,rst,dout);
inputdin;
inputclk;
inputrst;
outputdout;
regdout;
reg[7:0]x;
always@(posedge(clk)orposedge(rst))begin
if(rst==1'b1)
begin
dout=8'hzz;
end
else
begin
x={x[6:0],din};
dout=x[7];
end
end
endmodule

62. SIPO Shift Register
modulesipo(din,clk,rst,dout);
inputdin;
inputclk;
inputrst;
output[7:0]dout;
reg[7:0]dout;
reg[7:0]x;
always@(posedge(clk)orposedge(rst))
begin
if(rst)
dout=8'hzz;
else
begin
x={x[6:0],din};
dout=x;
end
end
endmodule

63. PIPO Shift Register
modulepipo(clk,rst,din,dout);
inputclk;
inputrst;
input[7:0]din;
output[7:0]dout;
reg[7:0]dout;
always@(posedge(clk)orposedge(rst))begin
if(rst==1'b1)
begin
dout=8'hzz;
end
else
begin
dout=din;
end
end
endmodule

64. Synchronous counter
modulesyncntr(clk,rst,q);
inputclk;
inputrst;
output[3:0]q;
reg[3:0]q;
reg[3:0]x=0;
always@(posedge(clk)orposedge(rst))
begin
if(rst==1'b1)
begin
q=4'b0;
end
else
begin
x=x+1'b1;
end
q=x;
end
endmodule