Unit 4 Part2-Input-output Subsystem.pptx

notes

1. INPUT/OUTPUT ORGANIZATION Department of Computer Engineering, PCCOE

2. Accessing I/Odevices Bu s I/ O de vice 1 I/ O de vic e n Processor Department of Computer Engineering, PCCOE Memory Multiple I/O devices may be connected to the processor and the memory via a bus. Bus consists of three sets of lines to carry address, data and control signals. E a c h I / O d e v i c e i s assign e d a n un i qu e add r e ss . To access an I/O device, the processor places the address on the address lines. The device recognizes the address, and responds to the control signals.

3. Accessing I/O devices (contd..) I/ O d e v i c e s an d t h e m e m o r y m a y s h a r e t h e s a m e a d d r e s s s p a c e : M e m o r y - m a p p e d I/O. A n y m a c h i n e i n s t r u c t i o n t h a t c a n a c c e s s m e m o r y c a n b e u s e d t o t r a n s f e r d a t a t o o r f r o m a n I / O d e v i c e . S i m p l e r s o f t w a r e . I/ O d e v i c e s and t h e m e m o r y m a y h a v e d i ff e r e n t a d d r e s s s p a c e s : S p e c i a l i n s t r u c t i o n s t o t r a n s f e r d a t a t o a n d f r o m I / O d e v i c e s . I / O d e v i c e s m a y h a v e t o d e a l wit h f e w e r a d d r e s s l i n es . I / O a d d r e s s l i n e s nee d n o t b e p h y s i c a l l y s e p a r a t e f r o m m e m o r y a d d r e s s l i n es . I n f a c t , a d d r e s s l i n e s m a y b e s h a r e d b e t w e e n I / O d e v i c e s a n d m e m o r y , wit h a c o n t r o l s i g n a l t o i n d i c a t e w h e t h e r i t i s a m e m o r y a d d r e s s o r a n I / O a d d r e s s .

4. Accessing I/O devices (contd..) I/ O i n er f ac t e Address decoder Data r egi st er s Control circuit Input de v ice Bu s I/ O d e v i c e i s c onn e c t e d t o th e bu s usin g a n I/ O i n t e r f a c e circ u i t wh ic h ha s : - Address decoder, control circuit, and data and status registers. Address decoder decodes the address placed on the address lines thus enabling the device to recognize its address. Data register holds the data being transferred to or from the processor. Status register holds information necessary for the operation of the I/O device. Data and status registers are connected to the data lines, and have unique addresses. • I / O i n t e r f a c e circ u i t c oo r d i na t D e e s p I / a O r t t m r a e n n s t f o e f r s C

5. Accessing I/O devices (contd..) Department of Computer Engineering, PCCOE R e c a l l t h a t t h e r a t e o f t r a n s f e r t o a n d f r o m I / O d e v i c e s is s l o w e r t h a n t h e s p e e d of t h e p r o c e s s o r . T h i s c r e a t e s t h e n e e d f o r m e c h a n i s m s t o s y n c h r o n i z e d a t a t r a n s f e r s b e t w e e n t h e m . P r o g r a m - c o n t r o l l e d I / O : P ro c e s s o r re p e at e d l y m o n i t o r s a status fl a g to a c h i e v e t h e n e c e s s a r y s ynch r o n i z a t i o n . P r o c e s s o r p o ll s t h e I / O d e vi c e . T w o o t h e r m e c h a n i s m s u s e d f o r s y n c h r o n i z i n g d a t a t r a n s f e r s b e t w e e n t h e p r o c e s s o r a n d m e m o r y : Interrupts. D i r e c t M e m o r y Acc ess .

6. Bu s arbi t ra t i o n Engineering, PCCOE P r o c e s s o r an d DM A c o n t r o l l e r s b o t h n e e d t o i n i t i a t e d a t a t r a n s f e r s o n t h e bus a n d a c c e s s m a i n m e m o r y. T h e d e v i c e that i s a l l o w e d to initiate t r a n s f e r s o n t h e bu s a t a n y g i v e n t i m e i s c a l l e d t h e bu s m a s t e r . W h e n t h e c u r r e n t m a s t e r r e l i n q u i s h e s i t s s ta t u s m a s t e r , a n o t h e r d e v i c e b u s as t h e bus c a n a c q u i r e this status. T h e p r o c e s s b y w h i c h t h e n e x t d e v i c e t o b e c o m e t h e b u s m a s t e r i s s e l e c t e d a n d bu s m a s t e r s h i p i s t r a n s f e r r e d t o i t i s c a l l e d b u s a r b i t r a t i o n . C e n t r a l i ze d arbitration: A s i n g l e bu s a r b i t e r p e r f o r m s t h e a r b i t r a t i o n . D i s t r i buted arbitration: A l l d e v i c e s p a r t i c D i p e p a a t r e t m i n e n t t h o e f C s o e m l p e u c t t e i r o n o f t h e n e x t bu s

7. Interface Circuits Department of Computer Engineering, PCCOE

8. Interface circuits Department of Computer Engineering, PCCOE I / O i n t e r f a c e c o n s i s t s o f th e c i r c u i t r y r e q u i r e d t o c o n n e c t a n I / O d e v i c e t o a c o m p u t e r bu s . S i d e of t h e i n t e r fa c e w h i c h c o n n e c t s to t h e c o m p u t e r h a s b u s s i g n a l s for: A d d r e s s , Data C o n t r o l S i d e of t h e i n t e r fa c e w h i c h c o n n e c t s to the I / O d e v i c e h a s : Data p at h a n d a s s o c i a t e d co nt ro l s to t ra n s fe r d a ta b e t w e e n t h e i n te r fa c e a n d t h e I/O d e v i c e . T h i s s i d e i s c a l l e d a s a “ po r t ” . Ports c a n be c l a s s i fi e d i nto two: P a r a l l e l p o rt , S e r i a l p o rt .

9. Interface circuits (contd..) Department of Computer Engineering, PCCOE Paral l e l p o r t t ra n s fe rs d ata in t h e f o r m of a n u m b e r of bits, n o r m a l l y 8 or 16 to or f r o m t h e d e v i c e . S e r i a l p o r t t r a n s f e r s an d r e c e i v e s d a t a o n e b i t a t a t i m e . P r o c e s s o r c o m m u n i c a t e s wi t h t h e bus i n the s a m e way, w h e t h e r it is a p a r a l l e l p o r t o r a s e r i a l p o r t . C o n v e r s i o n f r o m t h e p a r a l l e l t o s e r i a l a n d v i c e v e r s a t a k e s p l a c e i n s i d e t h e i n t e r f a c e c i r c u i t .

10. Parallel port V ali d Dat a K e y b o ar d Encod er an d debuger circuit SI N Inpu in t te r f a ce DATAIN Process or Dat a Addres s R / W M as t e r -read S l a v e -re a d - Slave-ready signal. Keyboard is connected to a processor using a parallel port. Pr o c e ss o r i s 32-b i t s an d us e s m e mo r y - m a p p e d I / O an d th e asynchronous bus protocol . On the processor side of the interface we have: Data lines. Address lines C o n t r o l o r R/ W li n e . Master-ready signal and

11. Seria l por t S e r i a l p o r t p r o c e s s o r i s u s e d t o c o n n e c t t h e t o I / O d e v i c e s t h a t r e q u i r e t r a n s m i s s i o n o f d a t a o n e bi t a t a t i m e . S e r i a l p o r t c o m m u n i c a t e s i n a bi t - s e r i a l fa s h i o n on t h e d e v i c e s i d e and bi t p a r a l l e l f a s h i o n o n t h e bu s s i d e . T r a n s f o r m a t i o n b e t w e e n t h e p a r a l l e l a n d s e r i a l f o r m a t s i s a c h i e v e d wit h sh i f t r e g i s t e r s t h a t h a v e p a ra l l e l a c c e s s capability.

12. Seria l por t (contd . .) S e r i a l i n t e r f a c e s r e q u i r e f e w e r w i r es , a n d h e n c e s e r i a l t r a n s m i s s i o n i s c o n v e n i e n t f o r c o n n e c t i n g d e v i c e s t h a t a r e p h y s i c a l l y d i s t a n t f r o m t h e c o m p u t e r . S p e e d of t r a n s m i s s i o n of t h e d ata o v e r a s e r i a l i n t e r fa c e is k n o w n as t h e “bit rate”. B i t r a t e depend s o n t h e n a t u r e o f t h e d e v i c e s c o n n e c t e d . In o r d e r to a c c o m m o d a t e d e v i c e s wi t h a r a n g e o f s p e e d s , a s e r i a l i n t e r f a c e m u s t b e abl e t o us e a r a n g e o f c l o c k s p e e d s . S e v e r a l s t a n d a r d s e r i a l i n t e r f a c e s h a v e b e e n d e v e l o p e d : U n i v e r s a l A s y n c h r o n o u s R e c e i v e r T r a n s m i t t e r ( U A R T ) f o r l o w - s p e e d s e r i a l d e v i c e s .

13. Standard I/O interfaces I / O d e v i c e i s c o n n e c t e d t o a c o m p u t e r u s i n g a n i n t e r fa c e c i rcuit. Do we h a v e to d e s i g n a d i ffe r e n t i n t e r fa c e for e v e r y c o m b i n a t i o n o f a n I / O d e v i c e a n d a c o m p u t e r ? A p r a c t i c a l a p p r o a c h i s t o d e v e l o p s t a n d a r d i nt e r fa c e s a n d protocols. A p e r s o n a l c o m p u t e r h a s : A m o t h e r b o a r d w h i c h h o u s e s t h e p r o c e s s o r c h i p , m a i n m e m o r y a n d s o m e I/ O i n t e r f a c e s . A f e w c o n n e c t o r s i nt o w h i c h a d d i t i o n a l i n t e r f a c e s c a n b e p l u g g e d . P r o c e s s o r bu s i s d e fi n e d b y th e s i g n a l s o n t h e p r o c e s s o r c h i p . D e v i c e s w h i c h r e q u i r e h i g h - s p e e d c o n n e c t i o n t o th e p r o c e s s o r

14. Standard I/O interfaces (contd..) A n u m b e r o f s t a n d a r d s h a v e b e e n d e v e l o p e d f o r t h e e x p a n s i o n bus . S o m e h a v e e v o l v e d b y d e f au lt . F o r e x a m p l e , IB M ’ s I n d u s t r y S t a n d a r d Architecture. T h r e e w i d e l y u s e d bu s s t a n d a r d s : P C I ( P e r i p h e r a l C o m p o n e n t I n t e r c o n n e c t ) S C S I ( S m a l l C o m p u t e r S y s t e m I n t e r f a c e ) U S B ( U n iv e r sa l S e r i a l B u s )

15. Standard I/O interfaces (contd..) Main memory Processor Bridge P roc ess or bus PCI bus A dd i t iona l memory CD-ROM controller Disk c o n tro l l er D i s k 1 D i s k 2 CD- R OM SCSI controller USB controller Vi de o Keyboard Game IDE disk SCSI u b s Ethernet Interface Expansion bus on the motherboard Bridge circuit translates signals and protocols from processor bus to PCI bus. ISA Interface

16. P C I Bus Peripheral Component Interconnect I n t r o d u c e d i n 199 2 L o w - c o s t bu s P r o c e s s o r i n d e p e n d e n t P l u g - a n d - p l a y c a p a b i l i t y I n t o d a y ’ s c o m p u t e r s , m o s t m e m o r y t r a n s f e r s i n v o l v e a bu r s t o f d a t a r a t h e r t h a n ju s t o n e w o r d . T h e P C I i s d e s i g n e d p r i m a r i l y t o s u p p o r t t h i s m o d e o f o p e r a t i o n . T h e bu s s u p p o r t s t h r e e i n d e p e n d e n t a d d r e s s s p a c e s : m e m o r y , I / O , a n d c o n fi g u r a t i o n . w e a s s u m e d t h a t t h e m a s t e r m a i n t a i n s t h e a d d r e s s i n f o r m a t i o n o n t h e b u s u n t i l d a t a t r a n s f e r i s c o m p l e t e d . Bu t , t h e a d d r e s s i s neede d o n l y l o n g e n o u g h f o r t h e s l a v e t o b e s e l e c t e d . T h u s , t h e a d d r e s s i s neede d o n t h e bu s f o r o n e c l o c k c y c l e o n l y , f r e e i n g t h e a d d r e s s l i n e s t o b e u s e d f o r s e n d i n g d a t a i n s u b s e q u e n t c l o c k c y c l e s . T h e r esu l t i s a s i g n i fi c a n t c o s t r e d u c t i o n . A m a s t e r i s c a l l e d a n i n i t i a t o r i n P C I t e r m i n o l o g y . T h e a d d r e s s e d d e v i c e t h a t r e s p o n d s t o r e a d a n d w r i t e c o m m a n d s i s c a l l e d a t a r g et .

17. S C S I B u s Department of Computer Engineering, PCCOE T h e a c r o n y m S C S I s t a n d s f o r S m a l l C o m p u t e r S y s t e m I nte r fa c e . I t r e f e r s t o a s t a n d a r d b u s d e fi n e d b y t h e A m e r i c a n National S t a n d a r d s Institute (ANSI) I n t h e o r i g i n a l s p e c i fi c a t i o n s o f t h e s t a n d a r d , d e v i c e s s u c h a s d i s ks a r e c o n n e c t e d to a c o m p u t e r v i a a 5 - w i r e c a b l e , w h i c h c a n b e u p t o 2 5 m e t e r s i n l e n g t h a n d c a n t r a n s f e r d a t a a t r a t e s u p t o 5 m e g a b y t e s / s . T h e S C S I b u s s t a n d a r d h a s u n d e r g o n e m a n y r ev i s i o n s , a n d i t s d a t a t r a n s f e r c a p a b i l i t y h a s i n c r e a s e d v e r y r a p i d l y , a l m o s t d o u b l i n g e v e r y two y e a r s . S C S I - 2 a n d S C S I - 3 h a v e b e e n d e fi n e d , a n d e a c h h a s s e v e r a l o p ti ons .

18. S C S I B u s (C o n t d., ) Department of Computer Engineering, PCCOE D e v i c e s c o n n e c t e d t o t h e S C S I b u s a r e n o t p a r t o f t h e a d d r e s s s p a c e o f t h e p r o c e s s o r T h e S C S I b u s i s c o n n e c t e d t o t h e p r o c e s s o r bu s t h r o u g h a S C S I c o n t r o ll e r . T h i s c o n t r o l l e r u s e s DM A t o t r a n s f e r d a t a p a c k e t s f r o m t h e m a i n m e m o r y to t h e d e v i c e , or v i c e v e rs a . A p a c k e t m a y c o n t a i n a b l o c k o f da t a , c o m m a n d s f r o m t h e p r o c e s s o r t o t h e d e v i c e , o r s t a t u s i n f o r m a t i o n a b o u t t h e d e v i c e . A c o n t r o l l e r c o n n e c t e d t o a S C S I bu s i s o n e o f t w o t y p e s – a n in i t iator or a target. A n i n i t i a t o r h a s t h e ab ili t y t o s e l e c t a p a r t i c u l a r t a r ge t a n d t o s e n d c o m m a n d s s p e c i f y i n g t h e o p e r a t i o n s t o b e p e r f o r m e d . T h e d i s k c o n t r o l l e r o p e r a t e s a s a t a r g e t . I t c a r r i e s o u t t h e c o m m a n d s it r e c e i v e s f r o m t h e initiator. T h e i n i t i a t o r e s t a b l i s h e s a l o g i c a l c o n n e c t i o n wit h t h e i n t e n d e d target. O n c e t h i s c o n n e c t i o n h a s bee n e s t a b l i s h e d , i t c a n b e s u s p e n d e d a n d re s t o re d as needed to t ra n s fe r c o m m a n d s a n d b u rsts of data. W h i l e a p a r t i c u l a r c o n n e c t i o n i s s u s p e n d e d , o t h e r d e v i c e c a n u s e t h e b u s to t ra n s fe r i n fo r m a t i o n . T h i s ab ili t y t o o v e r l a p d a t a t r a n s f e r r e q u e s t s i s o n e o f t h e k e y f e a t u r e s o f t h e S C S I bu s t h a t l e a d s t o i t s h i g h p e r f o r m a n c e .

19. S C S I B u s ( C o n td ., ) Department of Computer Engineering, PCCOE D a t a t r a n s f e r s o n t h e SCS I bu s a r e a l w a y s c o n t r o l l e d b y t h e t a r g e t controller. To s e n d a c o m m a n d to a target, an i n i t i a t o r r e q u e s t s c o n t r o l o f t h e bu s a n d , a f t e r w i n n i n g a r b it r a ti o n , s e l e c t s t h e c o n t r o l l e r i t an d h a n d s w a n t s t o c o m m u n i c a t e w i t h co nt ro l of t h e bus o v e r to it. T h e n t h e c o n t r o l l e r s t a r t s a d a t a t ra n s fe r o p e ra t i o n to r e c e i v e a c o m m a n d f r o m t h e initiator.

20. U S B Department of Computer Engineering, PCCOE U n i v e r s a l S e r i a l B u s ( U SB ) i s a n i n d u s t r y s t a n d a r d d e v e l o p e d t h r o u g h a c o l l a b o r a t i v e e ff o r t o f s e v e r a l c o m p u t e r a n d c o m m u n i c a t i o n c o m p a n i e s , i n c l u d i n g C o m p a q , H e w l e t t - P a c k a r d , Intel, L u c ent , Microsoft, Nortel Net wor ks, and Philips. S p e e d L o w - s p e e d ( 1 . 5 M b / s ) F u l l - s p e e d ( 1 2 Mb / s ) H i g h - s p e e d ( 4 8 Mb / s ) P o r t L i m i t a t i o n D e v i c e C h a r a c t e r i s t i c s P l u g - a n d - p l a y

21. H ost co m put e r R oot hub H ub d I/O v ice H ub d I/O e v ice d I/O v i c e H ub d I/O e v ice d I/O e v i c e d I/O e v ice Universal Serial Bus tree structure e e Department of Computer Engineering, PCCOE

22. Universal Serial Bus tree structure To a c c o m m o d a t e a l a r g e n u m b e r o f d e v i c e s that c a n b e a d d e d o r r e m o v e d a t a n y t i m e , t h e U S B h a s t h e t r e e s t r u c tu r e a s s h o w n i n t h e fi g u r e . E a c h n o d e o f t h e t r e e h a s a d e v i c e c a l l e d a hub , w h i c h a c t s a s a n i n t e r m e d i a t e c o n t r o l p o i n t b e t w e e n t h e h o s t a n d t h e I / O d e v i c e s . At t h e ro o t of t h e t r ee , a r o o t hu b c o n n e c t s t h e e n t i r e t r e e t o t h e h o s t c o m p u t e r . Th e l e a v e s o f t h e t r e e a r e t h e I / O d e v i c e s bein g s e r v e d ( f o r e x a m p l e , k e y b o a r d , I nt e r n e t c o n n e c t i o n , s p e a k e r , o r d i g i t a l T V ) In n o r m a l o p e rat i o n , a hub c o p i e s a m e s s a g e that it r e c e i v e s f r o m i t s u p s t r e a m c o n n e c t i o n t o a l l i t s d o w n s t r e a m p or t s . A s a r e s ult , a m e s s a g e s e n t b y t h e h o s t c o m p u t e r i s b r o a d c a s t t o a l l I / O d e v i c e s , bu t o n l y t h e a d d r e s s e d d e v i c e will r e s p o n d to that m e s s a g e . H o w e v e r , a m e s s a g e f r o m a n I / O d e v i c e i s s e n t o n l y u p s t r e a m t o w a r d s t h e r o o t o f t h e t r e e a n d i s n o t s e e n b y o t h e r d e v i c e s . H e n c e , t h e U S B e n a b l e s t h e h o s t to c o m m u n i c a t e w i th t h e I / O d e v i c e s , but it d o e s no t e n a b l e t h e s e d e v i c e s to