Unit II Shift Registers and Counters.pptx

SHift Registers and counters in digital logic and computer architecture

1. Shift Registers and Counters 12.07.2024

2. Serial in parallel out(SIPO) 2 CLK DATA OUTPUT Q A Q B Q C Q D 1 1 1 2 1 3 1 1 4 1 1 1

3. 3 Clock Pulse No QA QB QC QD 1 1 2 1 3 1 4 1 5

4. Parallel In serial out (PISO) 4

5. Bidirectional serial out

6. 6 / 28 Universal Shift Register Mode Control Register Operation S 1 S No change 1 Shift right 1 Shift left 1 1 Parallel load Q 3 Q 2 Q 1 Q D 3 D 2 D 1 D S 1 S USR CLR SR in SL in

7. 7