Verilog code

basic

1. codes

27. module d_flip_flop ( din ,clk ,reset ,dout );
output dout ;
reg dout;
input din ;
input clk ;
input reset ;
always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end
endmodule

28. module t_flip_flop ( t ,clk ,reset ,dout );
output dout ;
reg dout ;
input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
if (t)
dout <= ~dout;
end
end
endmodule

29. module SR_Latch ( s ,r ,enable ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input s,r,enable,reset ;
always @ (enable or s or r or reset) begin
if (reset) begin
q = 0;
qb = 1;
end else if (enable) begin
if (s!=r) begin
q = s;
qb = r;
end else if (s==1 && r==1) begin
q = 1'bZ;
qb = 1'bZ;
end
end
end
endmodule

30. module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input j,k,clk,reset ;
always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end
endmodule

31. •module Serial_in_Serial_out ( din ,clk ,reset ,dout );
output dout ;
reg dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [2:0]s;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
s[0] <= din ;
s[1] <= s[0] ;
s[2] <= s[1] ;
dout <= s[2];
end
end
endmodule

32. •module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
wire [3:0] dout ;
input din,clk,reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule

33. •module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule

34. •module PIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end
endmodule

35. •module siso ( din ,clk ,reset ,dout );
output dout ;
input din ;
input clk ;
input reset ;
wire [2:0]s;
d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));
d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));
d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));
d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));
endmodule