Very high speed HDL Presentation FOR KIET.pptx

vhdl codes

1. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_Gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end AND_Gate ; architecture Behavioral of AND_Gate is begin Y <= A and B; end Behavioral; AND Gate 2

2. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Half_Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Sum : out STD_LOGIC; Carry : out STD_LOGIC ); end Half_Adder ; architecture Behavioral of Half_Adder is begin Sum <= A xor B; Carry <= A and B; end Behavioral; Half Adder 3

3. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Full_Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC ); end Full_Adder ; architecture Behavioral of Full_Adder is begin Sum <= A xor B xor Cin ; Cout <= (A and B) or (B and Cin ) or ( Cin and A); end Behavioral; F ull adder 4

4. 4:1 multiplexer (MUX) 5 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX_4to1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(1 downto 0); Y : out STD_LOGIC ); end MUX_4to1; architecture Behavioral of MUX_4to1 is begin process(A, B, C, D, Sel ) begin case Sel is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= '0'; end case; end process; end Behavioral;

5. 2-to-4 decoder 6 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Decoder_2to4 is Port ( A : in STD_LOGIC_VECTOR(1 downto 0); Y : out STD_LOGIC_VECTOR(3 downto 0) ); end Decoder_2to4; architecture Behavioral of Decoder_2to4 is begin process(A) begin case A is when "00" => Y <= "0001"; when "01" => Y <= "0010"; when "10" => Y <= "0100"; when "11" => Y <= "1000"; when others => Y <= "0000"; end case; end process; end Behavioral;

6. 4-to-2 encoder 7 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Encoder_4to2 is Port ( D : in STD_LOGIC_VECTOR(3 downto 0); Y : out STD_LOGIC_VECTOR(1 downto 0); Valid : out STD_LOGIC ); end Encoder_4to2; architecture Behavioral of Encoder_4to2 is begin process(D) begin case D is when "0001" => Y <= "00"; Valid <= '1'; when "0010" => Y <= "01"; Valid <= '1'; when "0100" => Y <= "10"; Valid <= '1'; when "1000" => Y <= "11"; Valid <= '1'; when others => Y <= "00"; Valid <= '0'; end case; end process; end Behavioral;

7. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BCD_to_7Segment is Port ( BCD : in STD_LOGIC_VECTOR(3 downto 0); Segments : out STD_LOGIC_VECTOR(6 downto 0) ); end BCD_to_7Segment; architecture Behavioral of BCD_to_7Segment is begin process(BCD) begin case BCD is when "0000" => Segments <= "0000001"; when "0001" => Segments <= "1001111"; when "0010" => Segments <= "0010010"; when "0011" => Segments <= "0000110"; when "0100" => Segments <= "1001100"; when "0101" => Segments <= "0100100"; when "0110" => Segments <= "0100000"; when "0111" => Segments <= "0001111"; when "1000" => Segments <= "0000000"; when "1001" => Segments <= "0000100"; when others => Segments <= "1111111"; end case; end process; end Behavioral; Binary Coded Decimal (BCD) to 7-segment display decoder 8

8. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Priority_Encoder_4to2 is Port ( D : in STD_LOGIC_VECTOR(3 downto 0); Y : out STD_LOGIC_VECTOR(1 downto 0); Valid : out STD_LOGIC ); end Priority_Encoder_4to2; architecture Behavioral of Priority_Encoder_4to2 is begin process(D) begin if D(3) = '1' then Y <= "11"; Valid <= '1'; elsif D(2) = '1' then Y <= "10"; Valid <= '1'; elsif D(1) = '1' then Y <= "01"; Valid <= '1'; elsif D(0) = '1' then Y <= "00"; Valid <= '1'; else Y <= "00"; Valid <= '0'; end if; end process; end Behavioral; 4-to-2 priority encoder 9

9. SR Flip-Flop 10 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SR_FlipFlop is Port ( S : in STD_LOGIC; R : in STD_LOGIC; Q : out STD_LOGIC; Q_bar : out STD_LOGIC ); end SR_FlipFlop ; architecture Behavioral of SR_FlipFlop is begin process(S, R) begin if (S = '1' and R = '0') then Q <= '1'; Q_bar <= '0'; elsif (S = '0' and R = '1') then Q <= '0'; Q_bar <= '1'; elsif (S = '0' and R = '0') then -- Hold state else Q <= 'X'; -- Undefined state Q_bar <= 'X'; -- Undefined state end if; end process; end Behavioral;

10. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity JK_FlipFlop is Port ( J : in STD_LOGIC; K : in STD_LOGIC; CLK : in STD_LOGIC; RESET : in STD_LOGIC; Q : out STD_LOGIC; Q_bar : out STD_LOGIC ); end JK_FlipFlop ; architecture Behavioral of JK_FlipFlop is begin process(CLK, RESET) begin if RESET = '1' then Q <= '0'; Q_bar <= '1'; elsif rising_edge (CLK) then if J = '0' and K = '0' then Q <= Q; Q_bar <= Q_bar ; elsif J = '0' and K = '1' then Q <= '0'; Q_bar <= '1'; elsif J = '1' and K = '0' then Q <= '1'; Q_bar <= '0'; elsif J = '1' and K = '1' then Q <= not Q; Q_bar <= not Q_bar ; end if; end if; end process; end Behavioral; JK Flip-Flop 11

11. T Flip-Flop 12 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity T_FlipFlop is Port ( T : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC; Q_bar : out STD_LOGIC ); end T_FlipFlop ; architecture Behavioral of T_FlipFlop is signal Q_int : STD_LOGIC := '0'; begin process(CLK) begin if rising_edge (CLK) then if T = '1' then Q_int <= not Q_int ; end if; end if; end process; Q <= Q_int ; Q_bar <= not Q_int ; end Behavioral;

12. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FlipFlop is Port ( D : in STD_LOGIC; CLK : in STD_LOGIC; RESET : in STD_LOGIC; Q : out STD_LOGIC ); end D_FlipFlop ; architecture Behavioral of D_FlipFlop is begin process(CLK, RESET) begin if RESET = '1' then Q <= '0'; elsif rising_edge (CLK) then Q <= D; end if; end process; end Behavioral; D Flip-Flop 13

13. 4-bit Parallel Adder Code 14 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Parallel_4Bit_Adder is Port ( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); Cin : in STD_LOGIC; Sum : out STD_LOGIC_VECTOR(3 downto 0); Cout : out STD_LOGIC ); end Parallel_4Bit_Adder; architecture Behavioral of Parallel_4Bit_Adder is signal C : STD_LOGIC_VECTOR(4 downto 0); -- Carry signals begin C(0) <= Cin ; process(A, B, Cin ) begin Sum(0) <= A(0) XOR B(0) XOR C(0); C(1) <= (A(0) AND B(0)) OR (C(0) AND (A(0) XOR B(0))); Sum(1) <= A(1) XOR B(1) XOR C(1); C(2) <= (A(1) AND B(1)) OR (C(1) AND (A(1) XOR B(1))); Sum(2) <= A(2) XOR B(2) XOR C(2); C(3) <= (A(2) AND B(2)) OR (C(2) AND (A(2) XOR B(2))); Sum(3) <= A(3) XOR B(3) XOR C(3); Cout <= (A(3) AND B(3)) OR (C(3) AND (A(3) XOR B(3))); end process; end Behavioral;

14. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Parallel_Adder is Port ( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); Cin : in STD_LOGIC; Sum : out STD_LOGIC_VECTOR(3 downto 0); Cout : out STD_LOGIC ); end Parallel_Adder ; architecture Behavioral of Parallel_Adder is component Full_Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC ); end component; signal C : STD_LOGIC_VECTOR(3 downto 0); begin FA0: Full_Adder port map (A(0), B(0), Cin , Sum(0), C(0)); FA1: Full_Adder port map (A(1), B(1), C(0), Sum(1), C(1)); FA2: Full_Adder port map (A(2), B(2), C(1), Sum(2), C(2)); FA3: Full_Adder port map (A(3), B(3), C(2), Sum(3), C(3)); Cout <= C(3); end Behavioral; 15

15. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Universal_Shift_Register is Port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; LOAD : in STD_LOGIC; SHIFT_LEFT : in STD_LOGIC; SHIFT_RIGHT: in STD_LOGIC; SERIAL_IN : in STD_LOGIC; PARALLEL_IN : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0); SERIAL_OUT : out STD_LOGIC ); end Universal_Shift_Register ; architecture Behavioral of Universal_Shift_Register is signal reg : STD_LOGIC_VECTOR(3 downto 0); begin process(CLK, RESET) begin if RESET = '1' then reg <= (others => '0'); elsif rising_edge (CLK) then if LOAD = '1' then reg <= PARALLEL_IN; elsif SHIFT_LEFT = '1' then reg <= reg (2 downto 0) & '0'; elsif SHIFT_RIGHT = '1' then reg <= '0' & reg (3 downto 1); end if; end if; end process; DATA_OUT <= reg ; SERIAL_OUT <= reg (3); end Behavioral; Universal Shift Register VHDL Code 16

16. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Seat_Belt_Warning is Port ( Seat_Belt : in STD_LOGIC; -- Seat belt status (0: not fastened, 1: fastened) Ignition : in STD_LOGIC; -- Ignition status (0: off, 1: on) Warning : out STD_LOGIC -- Warning signal (0: no warning, 1: warning) ); end Seat_Belt_Warning ; VHDL Code for Seat Belt Warning System 17 architecture Behavioral of Seat_Belt_Warning is begin process( Seat_Belt , Ignition) begin if (Ignition = '1') then if ( Seat_Belt = '0') then Warning <= '1'; -- Warning if seat belt is not fastened else Warning <= '0'; -- No warning if seat belt is fastened end if; else Warning <= '0'; -- No warning if ignition is off end if; end process; end Behavioral;

17. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU is Port ( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); Op : in STD_LOGIC_VECTOR(2 downto 0); Result : out STD_LOGIC_VECTOR(3 downto 0); Carry : out STD_LOGIC; Zero : out STD_LOGIC ); end ALU; architecture Behavioral of ALU is begin process(A, B, Op) variable temp_result : STD_LOGIC_VECTOR(4 downto ); VHDL Code for a 4-bit ALU 18 begin case Op is when "000" => -- Addition temp_result := ('0' & A) + ('0' & B); Result <= temp_result (3 downto 0); Carry <= temp_result (4); when "001" => -- Subtraction temp_result := ('0' & A) - ('0' & B); Result <= temp_result (3 downto 0); Carry <= temp_result (4); when "010" => -- AND Result <= A and B; Carry <= '0'; when "011" => -- OR Result <= A or B; Carry <= '0'; when "100" => -- XOR Result <= A xor B; Carry <= '0'; when others => Result <= (others => '0'); Carry <= '0'; end case; if Result = "0000" then Zero <= '1'; else Zero <= '0'; end if; end process; end Behavioral;

18. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RAM_1bit is Port ( clk : in STD_LOGIC; en : in STD_LOGIC; wr : in STD_LOGIC; rd : in STD_LOGIC; addr : in STD_LOGIC; data_in : in STD_LOGIC; data_out : out STD_LOGIC); end RAM_1bit; architecture Behavioral of RAM_1bit is signal mem : STD_LOGIC ; begin process( clk ) begin if rising_edge ( clk ) then if en = '1' then if wr = '1' then if addr = '0' then mem <= data_in ; end if; end if; if rd = '1' then if addr = '0' then data_out <= mem ; end if; end if; end if; end if; end process; end Behavioral;

19. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DirectMappedCache is Generic ( CACHE_SIZE : integer := 4; -- Number of cache lines BLOCK_SIZE : integer := 1 -- Block size in words ); Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; addr : in STD_LOGIC_VECTOR(7 downto 0); data_in : in STD_LOGIC_VECTOR(7 downto 0); data_out : out STD_LOGIC_VECTOR(7 downto 0); wr : in STD_LOGIC; hit : out STD_LOGIC ); end DirectMappedCache ; architecture Behavioral of DirectMappedCache is type cache_line is record tag : STD_LOGIC_VECTOR(7 downto 2); data : STD_LOGIC_VECTOR(7 downto 0); valid : STD_LOGIC; end record; type cache_array is array (0 to CACHE_SIZE-1) of cache_line ; signal cache : cache_array := (others => (tag => (others => '0'), data => (others => '0'), valid => '0')); signal index : integer range 0 to CACHE_SIZE-1; signal tag : STD_LOGIC_VECTOR(7 downto 2); begin index <= CONV_INTEGER( addr (1 downto 0)); tag <= addr (7 downto 2);

20. process( clk , rst ) begin if rst = '1' then cache <= (others => (tag => (others => '0'), data => (others => '0'), valid => '0')); data_out <= (others => '0'); hit <= '0'; elsif rising_edge ( clk ) then if cache(index).valid = '1' and cache(index).tag = tag then hit <= '1'; data_out <= cache(index).data; if wr = '1' then cache(index).data <= data_in ; end if; else hit <= '0'; if wr = '1' then cache(index).tag <= tag; cache(index).data <= data_in ; cache(index).valid <= '1'; end if; data_out <= (others => '0'); end if; end if ; end process; end Behavioral;

21. THANK YOU !