VLSI _4_UNIT PPT FINAL.pdf ppt for design

Vlsi

2. Unit-IVGateLevelDesign:Switchlogic,Pass
transistors,transmissiongatesalternategatecircuits,
Pseudo-NMOSlogic,DifferentialCascadedVoltage
Staticlogic(DCVS)logic,Dynamiclogic,Domino
logic,ClockedCMOSlogic,Lowpowergates.

3. Subsystem Design
(Guide Lines to be Followed)

4. Take,forexample,thecaseofarelatively
straightforwardMSIlogiccircuitcomprising,say,500
transistors.Areasonabletimetoallocatetothedesign
andprovingofsuchacircuitcouldbesometwo
engineermonths.
Considernowthedesignofa500,000transistorVLSI
system.Evenifalinearrelationshipexistsbetween
complexityanddesigntime,therequireddesigntime
wouldbe2000engineer-monthsor170engineer-years.

5. 1. Define the requirements (properly and carefully).
2. Partition the overall architecture into appropriate
subsystems.
3. Consider communication paths carefully in order to
develop sensible interrelationships between subsystems.
4. Draw a floor plan of how the system is to map onto
the silicon (and alternate between 2, 3 and 4 as
necessary).

6. 5. Aim for regular structures so that design is largely
a matter of replication.
6. Draw suitable (stick or symbolic) diagrams of the
leaf-cells of the subsystems.
7. Convert each cell to a layout.
8. Carefully and thoroughly carry out a design rule
check on each cell.
9. Simulate the performance of each cell/subsystem.

7. Switchlogicisbasedonthe'passtransistor'oron
transmissiongates.Thisapproachisfastforsmall
arraysandtakesnostaticcurrentfromthesupplyrails.
Thus,powerdissipationofsucharraysissmallsince
currentonlyflowsonswitching.

8. Switch(passtransistor)logicissimilartologic
arraysbasedonrelaycontactsinthatthepath
througheachswitchisisolatedfromthesignal
activatingtheswitch.Inconsequence,thedesigner
hasaconsiderableamountoffreedomin
implementingarchitecturalfeaturescomparedwith
bipolarlogic-baseddesigns.

10. n-MOS transistor/ switch produces Strong ‘0’
but weak ‘1’

11. p-MOS transistor/ switch produces Strong ‘1’
but weak ‘0’

12. Transmission gate produces Strong
both strong‘1’ and strong ‘0’.

14. 2 Input NAND GATE (using n-MOS & CMOS Logic)

15. Other Forms of CMOS Logic

16. Pseudo-NMOS logic
Dynamic logic
Domino logic
Clocked CMOS logic
Differential Cascaded Voltage Static logic (DCVS)
logic

17. Pseudo-nMOSlogic

18. Clearly,ifwereplacethedepletionmodepull-up
transistorofthestandardnMOScircuitswithap-
transistorwithgateconnectedtoVss,wehavea
structuresimilartothenMOSequivalent.
1.Powerdissipationisreducedtoabout60%ofthat
associatedwiththecomparablenMOSdevice.
2.Owingtothehigherpull-upresistance,theinverter
pairdelayislargerbyafactorof8.5:5thanthe4:1
minimumsizenMOSinverter.

19. Dynamic CMOS logic
Φ=0, pre charge stage
Φ=1, evaluation stage
3 Input NAND GATE

20. Theactuallogicisimplementedintheinherentlyfaster
nMOSlogic(then-block);ap-transistorisusedforthe
non-time-criticalprechargingoftheoutputline'Z'sothat
theoutputcapacitanceischargedtoVDDduringtheoff
periodoftheclocksignal.
Duringthissameperiodtheinputsareappliedtothen-
blockandthestateofthelogicisthenevaluatedduring
theonperiodoftheclockwhenthebottomn-transistoris
turnedon.

21. Theoutputvoltagelevelisstoredinacapacitorduringthe
prechargephaseoftheclockcycle,andthenevaluated
duringtheevaluationphase.DynamicCMOSlogichas
highspeed,lowarea,andsimplelayout.However,italso
hassomechallenges,suchashighpowerdissipation,low
noisemargin,andlowfan-out.

22. Clocked CMOSlogic

25. Advantages of Clocked CMOS Logic
Predictable Timing
Simplified Sequential Design
Ease of Design and Debugging
Improved Signal Integrity
Disadvantages of Clocked CMOS Logic
Increased Power Consumption
Clock Skew and Jitter
Area Overhead
Latency
Design Complexity

26. CMOSdomino logic

28. 2 INPUT NAND GATE

29. 1.Suchlogicstructurescanhavesmallerareasthan
conventionalCMOSlogic.
2.Parasiticcapacitancesaresmallersothathigher
operatingspeedsarepossible.
3.Operationisfreeofglitchessinceeachgatecanmake
onlyone'1'to'0'transition.
4.Onlynon-invertingstructuresarepossiblebecauseof
thepresenceoftheinvertingbuffer.
5.Chargedistributionmaybeaproblemandmustbe
considered.

30. DCVSLogic
•DCVS -Differential
Cascode Voltage
Switch
•Differential inputs,
outputs
•Two pulldownnetworks
•Tradeoffs
–Lower capacitative
loading than static
CMOS
–No ratioed logic
needed
–Low static
power
consumption
–More transistors
–More signals toroute
betweengates
OUT
Pulldown
Network
OUT’
OUT’
Pulldown
Network
OUT
A
B
C
A’
B’
C’

31. DCVS logic: BARABY ABY

32. Advantages of DCVS Logic
•High-Speed Operation
•Low Power Consumption
•Reduced Noise Sensitivity
•Better Signal Integrity
Disadvantages of DCVS Logic
Increased Complexity
Design complexity/Area overhead

33. Low Power Gates

34. Introduction
Definition:What are low power gates?
Importance:Why is low power design crucial in
modern electronics?
Power Consumption in Digital Circuits
Dynamic Power Consumption:Switching activity,
capacitive load
Static Power Consumption:Leakage currents,
subthreshold leakage

35. Techniques for Low Power Design
Voltage Scaling:Lowering supply voltage
Clock Gating:Reducing clock signal to idle portions
of the circuit
Power Gating:Shutting off power to inactive blocks
Multi-Threshold CMOS (MTCMOS):Using
transistors with different threshold voltage

36. Types of Low Power Gates
Standard CMOS Gates:Basic CMOS inverter,
NAND, NOR
Sub-threshold Gates:Operating at voltages below
the threshold voltage
Adiabatic Logic Gates:Energy recovery logic
FinFETTechnology:Reducing leakage current
and dynamic power

37. AFinFETisatypeoffield-effecttransistor(FET)that
hasathinverticalfininsteadofbeingcompletely
planar.Thegateisfully“wrapped”aroundthe
channelonthreesidesformedbetweenthesourceand
thedrain.

38. Planar transistors vs. finFETsvs. gate-all-around Source: Lam
Research