vlsi fabrication

ic design and fabrication

1. Vlsi Design Process steps in IC fabrication

2. Process steps in IC fabrication The process of IC fabrication involves several steps such as :- Silicon wafer preparation Diffusion of impurities ion implantation Annealing process Oxidation process Lithography Chemical Vapour Deposition Epitaxial growth Reactors metallization Patterning Wire bonding Packaging

3. Silicon wafer preparation Silicon wafer manufacturing process has different steps for the formation of a large, perfect silicon crystal . Step 1:- Obtaining the Sand The sand (SiO 2 ) used to grow the wafers has to be a very clean and good form of silicon commonly called as quartzite. Step 2:- Preparing the Molten Silicon Bath The SiO2 reacts with excess C to first form SiC. At high temperature, the SiC reduces SiO2 to form Si. SiC (s) + SiO2 (s) → Si (l) + SiO (g) + CO (g) Si is reacted with HCl gas to form tricholorosilane , which is in gaseous form. Si (s) + 3HCl (g) → SiHCl3 (g) + H2 (g)

4. Silicon wafer preparation The trichlorosilane gas is removed and then reduced using H2 gas to obtain pure form of silicon 2SiHCl3 (g) + 2H2 (g) → 2Si (s) + 6HCl (g) Process can be cycled to increase purity of the formed Si. The final material obtained is called as EGS (Electronic grade silicon).

5. Silicon wafer preparation Step 3:- Making the Ingot There are two main techniques for converting polycrystalline silicon into a single crystal ingot, which are used to obtain the final wafers. Czochralski technique (CZ) This is the dominant technique for manufacturing single crystals. It is especially suited for the large wafers that are currently used in IC fabrication. Electronic grade silicon (EGS), which is melted in the furnace by heating above 1500 ◦C. A seed crystal is dipped in molten silicon and rotated slowly to extracted single crystal from a pool of molten Si. It requires careful control to give crystal desired purity and dimentiond

6. Silicon wafer preparation

7. Silicon wafer preparation

8. Silicon wafer preparation

9. Silicon wafer preparation Float zone technique This is mainly used for small sized wafers. The float zone technique is used for producing specialty wafers that have low oxygen impurity concentration. The basic feature of this growth technique is that the molten part of the sample is supported by the solid part. A rod of high purity polycrystalline material is held in a chuck while a metal coil is driven by a high power radio frequency signal is slowly passed along the length. The molten silicon at the seed end starts to freeze, forming the same crystal orientation as the seed crystal. After the heating coils move over the whole polysilicon rod, it converts to a single crystal silicon ingot.

10. Silicon wafer preparation

11. Silicon wafer preparation Step 4:- Preparing the Wafers Cutting Of Ingot Ingot is ground into the correct diameter for the wafers, the silicon ingot is sliced into very thin wafers. This is usually done with a diamond saw. Each of these wafers will then go through polishing until they are very smooth and just the right thickness. Lapping & Etching Processes Lapping removes the surface silicon which has been cracked or otherwise damaged by the slicing process, and assures a flat surface. Wafers are then etched in a chemically active reagent to remove any crystal damage remaining from the previous process step.

12. Silicon wafer preparation Step 5:- Polishing Process Polishing is a chemical/mechanical process that smoothes the uneven surface left by the lapping and etching processes and makes the wafer flat and smooth enough to support optical photolithography. Step 6:- Final Dimensional and Electrical Properties Qualification The wafers undergo a final test, performed in order to demonstrate conformance with customer specification for flatness, thickness, resistivity and type. Process induced defect and defect trend information is used by the wafer manufacturer for yield and process management of the immediately preceding steps

13. Silicon wafer preparation

14. Diffusion of impurities Diffusion and ion implantation are the two key processes to introduce a controlled amount of dopants into semiconductors and to alter the conductivity type. The process of junction formation, that is transition from p to n type or vice versa, It is typically accomplished by the process of diffusing the appropriate dopant impurities in a high temperature furnace. Impurity atoms are introduced onto the surface of a silicon wafer and diffuse into the lattice because of their tendency to move from regions of high to low concentration

15. Diffusion of impurities Diffusion of impurities is usually carried out at high temperatures (1000–1200°C) to obtain the desired doping profile. When the wafer is cooled to room temperature, the impurities are essentially “frozen” in position. There are mainly two types of physical mechanisms by which the impurities can diffuse into silicon wafer Substitutional Diffusion Interstitial Diffusion

16. Diffusion of impurities Substitutional Diffusion At high temperature many atoms in the semiconductor move out of their lattice site, leaving vacancies into which impurity atoms can move. The impurities, thus, diffuse by this type of vacancy motion and occupy lattice position in the crystal after it is cooled. Substitutional diffusion takes place by replacing the silicon atoms of parent crystal by impurity atom. Substitutional diffusion mechanism is applicable to the most common diffusants , such as boron, phosphorus, and arsenic.

17. Diffusion of impurities Interstitial Diffusion The impurity atom does not replace the silicon atom, but instead moves into the interstitial voids in the lattice. The main types of impurities diffusing by such mechanism are Gold, copper, and nickel. Gold, particularly, is introduced into silicon to reduce carrier life time and hence useful to increase speed at digital IC’s. The diffusion rate due to this process is very slow at room temperature but becomes practically acceptable at normal operating temperature of around 1000 degree Celsius

18. Diffusion of impurities

19. Fick’s Laws of Diffusion Fick’s law of diffusion explains about diffusion process (movement of molecules from higher concentration to lower concentration region) to solve diffusion coefficient derived by Adolf Fick in the year 1855. There are two laws that are interrelated i.e.; Fick’s first law is used to derive Fick’s second law which is similar to the diffusion equation. Fick’s first law Movement of solute from higher concentration to lower concentration across a concentration gradient. Where, J: diffusion flux D: diffusivity φ: concentration x: position

20. Diffusion of impurities Fick's Second Law of Diffusion . Fick's 2nd law of diffusion describes the rate of accumulation (or depletion) of concentration within the volume as proportional to the local curvature of the concentration gradient. The local rule for accumulation is given by Fick's 2nd law of diffusion: in which the accumulation, dC / dt [cm -3  s -1 ], is proportional to the diffusivity  [cm 2 /s] and the 2nd derivative (or curvature) of the concentration,  [cm -3  cm -2 ] or [cm -5 ].

21. ion implantation It is defined as the process by which impurity ions are accelerated to high velocity and physically lodged into the target material. In this process a beam of impurity ions is accelerated to kinetic energies in the range of several tens of kV and is directed to the surface of the silicon. As the impurity atoms enter the crystal, they give up their energy to the lattice in collisions and finally come to rest at some average penetration depth, called the projected range expressed in micro meters.

22. ion implantation A gas containing the desired impurity is ionized within the ion source. The ions are generated and repelled from their source in a diverging beam that is focussed before if passes through a mass separator that directs only the ions of the desired species through a narrow aperture. A second lens focuses this resolved beam which then passes through an accelerator that brings the ions to their required energy before they strike the target and become implanted in the exposed areas of the silicon wafers. The accelerating voltages may be from 20 kV to as much as 250 kV. In some ion implanters, the mass separation occurs after the ions are accelerated to high energy. Because the ion beam is small, means are provided for scanning it uniformly across the wafers. For this purpose the focussed ion beam is scanned electrostatically over the surface of the wafer in the target chamber.

23. ion implantation

24. Annealing process It is the process of repairing implant damage is called annealing. It puts dopant atoms in substitutional sites where they will be electrically active. There 2 objectives of annealing:- 1. healing, recrystallization ( 500-600 C) 2. Renew electrical activity (600-900 C) Its parameters that get most affected are conductivity the mobility and the life time Annealing is divided into 2 classes Pre- amorphised No-pre- amorphised

25. Annealing process

26. Annealing process

27. Annealing process

28. Annealing process

29. Annealing process

30. Oxidation process Oxidation is the process by which a layer of silicon dioxide is grown on the surface of a silicon wafer. It protects the junction from moisture and other atmospheric contaminants. It serves as an insulator on the water surface. Its high relative dielectric constant, which enables metal line to pass over the active silicon regions. It is used to isolate one device from another. Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere such as oxygen or water vapor . Si+02 = SiO 2  (solid)

31. Oxidation process There are two main growth mechanisms:- Dry oxidation – Si reacts with O2 to form SiO2. Si (s) + O2 (g) → SiO2 (s) Wet oxidation – Si reacts with water (steam) to form SiO2. Si (s) + 2H2O (g) → SiO2 (s) + 2H2 (g) Dry and wet oxidation need high temperature (900 - 1200 ◦C) for growth, though the kinetics are different, which is why this process is called thermal oxidation

32. Oxidation process The rate of diffusion of O 2  or H 2 O through the oxide layer will be inversely proportional to the thickness of the layer, so that we will have that dx / dt = C/x where “ x” is the oxide thickness and C is a constant of proportionality => xdx =   Cdt Integrating this equation both sides yields, x 2 /2 = Ct Solving for the oxide thickness x gives, x = √2Ct

33. Lithography Lithography is the process of transferring patterns of geometric shapes in a mask to a thin layer of radiation-sensitive material (called resist) covering the surface of a semiconductor wafer. Create a pattern with the dimensions established by the circuit design . Place the pattern correctly with respect to the crystal orientation and other existing patterns. The Lithography starts with the process of placing a photoresist (PR) layer over a wafer

34. Lithography

35. Lithography Photo lithography Process T he silicon wafer is uniformly coated with photoresist which is done by two ways Spray coating :- PR is sprayed over the wafer using PR spraying machine. Spin coating:- In this process the PR is put on the wafer and then spun at a high speed. The PR is made of organic material and it is of two types P ositive Photoresist layer Negative Photoresist layer

36. Lithography Positive Photoresist layer In Positive resists, the resist is exposed with UV light wherever the underlying material is to be removed. In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer. The exposed resist is then washed away by the developer solution, leaving windows of the bare underlying material. Negative Photoresist layer In Negative resists , the resist is exposed to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. Therefore , the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions. Masks used for negative photoresist, therefore, contain the inverse (or photographic "negative") of the pattern to be transferred.

37. Lithography Mask Alignment and Exposure One of the most important steps in the photolithography process is mask alignment. A mask or " photomask " is a square glass plate with a patterned emulsion of metal film on one side. The mask is aligned with the wafer, so that the pattern can be transferred onto the wafer surface. Each mask after the first one must be aligned to the previous pattern. Once the mask has been accurately aligned with the pattern on the wafer's surface, the photoresist is exposed through the pattern on the mask with a high intensity ultraviolet light. There are three primary exposure methods: contact, proximity, and projection

38. Lithography

39. Lithography Contact Printing In contact printing, the resist-coated silicon wafer is brought into physical contact with the glass photomask . The wafer is held on a vacuum chuck, and the whole assembly rises until the wafer and mask contact each other. The photoresist is exposed with UV light while the wafer is in contact position with the mask. Because of the contact between the resist and mask, very high resolution is possible in contact printing (e.g. 1-micron features in 0.5 microns of positive resist). The problem with contact printing is that debris, trapped between the resist and the mask, can damage the mask and cause defects in the pattern.

40. Lithography 2. Proximity Printing The proximity exposure method is similar to contact printing except that a small gap, 10 to 25 microns wide, is maintained between the wafer and the mask during exposure. This gap minimizes (but may not eliminate) mask damage. Approximately 2- to 4-micron resolution is possible with proximity printing. 3. Projection Printing Projection printing, avoids mask damage entirely. An image of the patterns on the mask is projected onto the resist-coated wafer, which is many centimeters away. In order to achieve high resolution, only a small portion of the mask is imaged. This small image field is scanned or stepped over the surface of the wafer. Projection printers that step the mask image over the wafer surface are called step-and-repeat systems. Step-and-repeat projection printers are capable of approximately 1-micron resolution.

41. Etching

42. Etching

43. Etching

44. Etching

45. Etching

46. Etching

47. Etching

48. Etching

49. Etching

50. Chemical Vapour Deposition ( cvd ) Chemical Vapor Deposition (CVD)  is the deposition of a solid material onto a heated substrate through decomposition or chemical reaction of compounds contained the gas passing over the substrate. Many materials such as, silicon nitride, silicon dioxide, non-crystalline silicon, and single crystal silicon, can be deposited through CVD method. A special method in CVD, called Epitaxy or Epitaxial Layer Deposition or Vapor -Phase Epitaxy (VPE), has only a single-crystal form as the deposited layer . This process is usually carried out for certain combinations of substrate and layer materials and under special deposition conditions.

51. Chemical Vapour Deposition ( cvd ) In CVD process, a reaction chamber is introduced in which the materials to be deposited are  passed through. These materials should be in the gaseous or vapor phase and react on or near the surface of the substrates, which are at some elevated temperature. This produces a chemical reaction and forms atoms or molecules that are to be deposited on entire substrate surface. A number of different materials can be deposited by the CVD process. These are listed below: Silicon epitaxial layer on a single-crystal silicon substrate ( homoepitaxy or commonly referred to as epitaxy ). Silicon epitaxial layer deposition on a sapphire ( Heteroepitaxy ). Silicon dioxide deposition. Silicon nitride deposition.

52. Chemical Vapour Deposition ( cvd ) CVD Reactors The most common deposition methods are Atmospheric-pressure chemical vapor deposition ( APCVD) Low-pressure chemical vapor deposition (LPCVD) Plasma-enhanced chemical vapor deposition (PECVD) or plasma deposition

53. Chemical Vapour Deposition ( cvd )

54. Chemical Vapour Deposition ( cvd ) Atmospheric-pressure chemical vapor deposition (APCVD ) Dielectric and poly-silicon films have been deposited at atmospheric pressure with the use of different types of reactors. But the use of such  Atmospheric-Pressure Reactors  have caused problems like low wafer throughput, and also require excessive wafer handling during loading and unloading, and provide uniformity in thickness . As time passed by, they have been replaced by low-pressure, hot-wall reactors. The major advantages of low-pressure CVD processes are Uniform step coverage Precise control of composition and structure Low temperature processing Fast deposition rates High throughput Low processing costs

55. Chemical Vapour Deposition ( cvd ) Low-pressure chemical vapor deposition (LPCVD ) Diagram [a] shows an LPCVD reactor that is used to deposit polysilicon , silicon dioxide, and silicon nitride. The reactor consists  of a quartz tube heated by a three-zone furnace. Te gas is introduced through one end of the furnace and pumped out f the other. The pressures inside the reaction chambers vary from 30 to 250 Pa, with a temperature range between 300 and 900 degree Celsius. Wafers  are kept in a quartz holder and are kept to stand in the vertical position, and perpendicular to the gas flow . Advantages – LPCVD Reactor Excellent uniformity, Large load size Ability to accommodate large diameter wafers Disadvantages – LPCVD Reactor Low deposition rate Frequent use of toxic corrosive or flammable gases

56. Chemical Vapour Deposition ( cvd ) Plasma-Enhanced CVD (PECVD) Diagram [c] shows a  Plasma-Enhanced CVD (PECVD)  or  Plasma Deposition Reactor  which is a radial-flow, parallel-plate type.  The reaction chamber is a cylinder, usually glass or aluminium, with aluminium, plates on the top and bottom. Samples lie on the grounded bottom electrode. An RF voltage is supplied to the top electrode so as to create a glow discharge between the two plates. This causes the gases to flow radially through the discharge. These gases begin at the outer edge and take the direction towards the centre. But,  if needed the pattern of the flow can also be reversed.

57. Chemical Vapour Deposition ( cvd ) Benefits of Chemical Vapour Deposition: Low temperature growth process. Fast deposition rate (especially APCVD ). Does not have to be a silicon substrate. Good step coverage (especially PECVD).

58. Epitaxial growth Epitaxy is referred to as an arrangement of atoms in a crystal form upon a crystal substrate, so that the resulting added layer structure is an exact extension of the substrate crystal structure. Deposited atoms arrange themselves along existing planes of the crystalline substrate material. This will cause the deposited atoms to bond to the parent atoms to form an unbroken chain of the crystal structure. The structure of the grown epitaxial layer is thus a continuation of that single-crystal substrate.

59. Epitaxial growth Epitaxial Growth of Silicon There are a number of different chemical reactions that can be used for the deposition of epitaxial layers. Four silicon sources have been used for growing epitaxial silicon. These are silicon tetrachloride [SiCl 4 ], dichlorosilane [SiH 2 Cl 2 ], trichlorosilane [SiHCl 3 ] and silane [SiH 4 ]. Silicon tetrachloride has been the most studied and has seen the widest industrial use. The overall reaction can be classed as a hydrogen reduction of a gas. SiCl 4  [gas] + 2H 2  [gas] = Si [solid] + 4HCl [gas] For understanding the above reaction, we should determine for the Si – CI – H system the equilibrium constant for each possible reaction and the partial pressure of each gaseous species at the temperature of interest. Equilibrium calculations reveal fourteen species to be in equilibrium with solid silicon. In practice many of the species can be ignored because their partial pressures are less than 10 -6  atm.

60. Epitaxial growth