VLSI Fabrication Process in detail pdf file

VLSI for UG and PG

1. Introduction
t
o
VLSI Fabrication Technologies
27/09/2005
Emanuele
B
aravelli

2. 2
Organization
„
Materials
U
sed
in VLSI Fabrication
„
VLSI Fabrication
T
echnologies
„
Overview
of Fabrication
M
ethods
„
Device
simulation

3. 3
Main
Categories
o
f Materials
Materials
c
an be
classified
into
three
m
ain
groups
r
egarding
their
e
lectrical
conduction
properties: „
Insulators
„
Conductors
„
Semiconductors

4. 4
Conductors
Conductors
a
re used
in IC design for
e
lectrical
connectivity. The following
are good
conducting
elements: „
Silver
„
Gold
„
Copper
„
Aluminum
„
Platinum

5. 5
Insulators
Insulators
are used
to
isolate conducting
and/or
semi-conducting
materials
f
rom
e
ach
o
ther.
MOS devices
and Capacitors
r
ely
on an
insulator
f
or
their
physical
operation.
The choice
of the insulators
(and the conductors)
in IC design depends
heavily
on how
t
he materials
interact
with
each
o
ther, especially
with
the
semiconductors.

6. 6
Semiconductors
„
The basic semiconductor material used
in device
fabrication
is
Silicon
„
The success of this
material is
due to:
…
Phisical
c
haracteristics
…
Abundance in nature and very low cost
…
Relatively easy process
…
Reliable high volume fabrication
„
Other
s
emiconductors
(e.g. GaAs) are used
for
s
pecial applications

7. 7
Organization
„
Materials
U
sed
in VLSI Fabrication
„
VLSI Fabrication
T
echnologies
„
Overview
of Fabrication
M
ethods
„
Device
simulation

8. 8
Overview
of Processing
Technologies
Although
a
number
of processing technologies
a
re
available, the majority of the production is
done
with
traditional
C
MOS. Other
processes
a
re limited
to
areas
where
C
MOS is
not
very
suitable
(like
h
igh speed
R
F applications)
B
i
pola
r
:
2%
S
O
I:
1
%
Ga
A
s
:
2
%
C
M
O
S
:
90%
Bi
CM
O
S
:

5%

9. 9
CMOS technology
„
An
Integrated Circuit (IC)
is an
electronic network fabricated in a single piece of a semiconductor material
„
The semiconductor surface is subjected to various processing steps in which impurities and other materials are added with specific geometrical patterns
„
The fabrication steps are sequenced to form three dimensional regions that act as transistors and interconnects that form the network

10. 10
Simplified
View
of MOSFET

11. 11
CMOS Process
The CMOS process
a
llows
f
abrication
of nMOS
and pMOS
transistors
s
ide-by-side
on the same
Silicon
substrate.

12. 12
Organization
„
Materials
U
sed
in VLSI Fabrication
„
VLSI Fabrication
T
echnologies
„
Overview
of Fabrication
M
ethods
„
Device
simulation

13. 13
Fabrication process sequence
„
Silicon manifacture
„
Wafer processing
…
Lithography
…
Oxide growth and removal
…
Diffusion and ion implantation
…
Annealing
…
Silicon deposition
…
Metallization
„
Testing
„
Assembly and packaging

14. 14
Single Crystal
Growth
(I)
„
Pure silicon
is
m
elted
in a
pot (1400
º
C) and a small
seed
containing
the
desired
crystal
o
rientation
is
inserted
into
molten
silicon
and slowly
(1mm/minute) pulled
out.

15. 15
Single Crystal
Growth
(II)
„
The silicon
crystal
(
in some
cases
a
lso
c
ontaining
d
oping)
is
manufactured
a
s
a
cylinder
(
ingot
) with
a diameter
of
8-12 inches
(1”=2.54
cm).
„
This
cylinder
is
carefully
sawed
into
t
hin
(
0.50-0.75
mm thick) disks
c
alled
wafers
, which
a
re later
polished
and marked
for
crystal
orientation.

16. 16
Lithography
(
I)
Lithography
: process used to transfer patterns to
each layer of the IC Lithography sequence steps: „
Designer
:
…
Drawing the “layer” patterns on a layout editor
„
Silicon Foundry
:
…
Masks generation from the layer patterns in the design data base
…
Printing: transfer the mask pattern to the wafer surface
…
Process the wafer to physically pattern each layer of the IC

17. 17
Lithography
(
II)
1.
Photoresist
a
pplication:
…
the surface to be patterned is spin-coated with a light-sens
itive
organic poly
m
er called photoresist
2.
Printing (exposure):
…
the mask pattern is developed on the photoresist, with UV light expos
ure
…
depending on the ty
pe of photoresist
(negative or positive), the expos
ed or
unexposed parts become resistant to certain types of solv
ents
3.
Development:
…
the soluble photoresist
is chemically
removed
…
The developed photoresist
acts
as a mask
for patterning of underly
ing layers and
then is removed.
1.
Phot
oresi
st
coat
i
n
g
Si
O
2
Phot
o
r
es
is
t
Sub
s
t
r
at
e
3.
Devel
opment
Sub
s
t
r
at
e
Sub
s
t
r
at
e
Ma
sk
Ult
r
a v
iolet
l
ight
O
p
a
que
Expose
d
Unex
pos
ed
2. E
x
po
s
u
re

18. 18
Oxide
G
rowth
/
Oxide
D
eposition
„
Oxide can be
grown
from silicon
through heating in an oxidizing atmosphere
…
Gate oxide, device isolation
…
Oxidation consumes silicon
„
SiO
2
is
deposited
on materials other than silicon
through reaction between gaseous silicon compounds and oxidizers
…
Insulation between different
layers of metallization
X
FO
X
0.54
X
FO
X
0.46
X
FO
X
Si
licon waf
e
r
S
ilic
o
n
s
u
r
f
a
c
e
Fi
el
d oxi
d
e

19. 19
Etching
„
Once the desired shape is patterned with photoresist, the
etching
process
allows unprotected materials to be removed
…
Wet etching
: uses chemicals
…
Dry or plasma etching
: uses ionized
gases

20. 20
Diffusion
a
nd Ion
I
mplantation
Doping materials
a
re added
to
change
t
he electrical
characteristics
of silicon
locally
through:
„
Diffusion
: dopants
deposited on silicon
move through the lattice by thermal diffusion (high temperature process)
…
Wells
„
Ion implantation
: highly energized
donor or acceptor atoms impinge on the surface and travel below it
…
The patterned SiO
2
serves as an
implantation mask
…
Source and Drain regions

21. 21
Annealing
Thermal annealing
is a high temperature
process which: „
allows doping impurities to diffuse further into the bulk
„
repairs lattice damage caused by the collisions with doping ions

22. 22
Silicon Deposition and Metallization „
Films of silicon can be added on the surface of a wafer
…
Epitaxy
: growth
of a single-crystal
semiconductor film on a crystalline substate
…
Polysilicon
: polycrystalline film
with a granular structure obtained through deposition
of silicon on an
amorphous material
„
MOSFET gates
„
Metallization: deposition of metal layers by evaporation
…
interconnections

23. 23
Advanced CMOS processes
„
Shallow trench isolation
„
source-drain halos (series resistance)
„
Self-aligned silicide (spacers)
„
…
n-wel
l
p+
p+
n+
n+
p
-
do
pi
n
g
n-d
oping
S
ilic
ide
Oxi
d
e spa
c
er
n+ po
ly
p+
po
ly
Sh
allow
-
tren
ch iso
latio
n
p
-
typ
e
substrate
Source-dr
a
in
ext
e
n
s
io
n

24. 24
Organization
„
Materials
U
sed
in VLSI Fabrication
„
VLSI Fabrication
T
echnologies
„
Overview
of Fabrication
M
ethods
„
Device
simulation

25. 25
MOS device simulation
„
2D 0.18 µm n-channel
MOS, tox
=
4 nm
„
Id
(Vds) simulation, Vgs=1.3V
„
8 re
finement
cycles
„
Refinement
on
ψ
,
n ,
p

26. 26
Research
activities
„
Geometrical
issues:
…
Sophisticated 2D geometries
(2nd generation
wavelets)
…
3D geometries
„
Simulation
issues:
…
Advanced
m
odels
(hydrodynamic, quantum effects)

27. 27
Links
„
http://humanresources.web.cern.ch/Humanresources/ external/training/tech/special/ELEC2002/ ELEC-2002_11Apr02_3.ppt
„
http://lsmwww.epfl.ch/Education/
„
http://lsiw
w
w.epfl.ch/LSI2001/teaching/webcourse/toc.
html
„
www.latticepress.com/prologvol1.html