Von Neumann Architecture 1 Computer Organisation Loren Al Hamwi
2 What are the important features of Von Neumann Architecture? Why is processor speed limited in the Von Neumann Architecture? How does the Fetch-Decode-Execute cycle work?
What is Von Neumann Architecture? Digital Computer- 4 parts: Processor design (Arithmetic & control units + along with internal memory) Memory to store data and instructions I/O devices Secondary storage 3
Processor Main Memory Arithmetic & Logic Unit Control Unit Input Devices Output Devices Mass Storage 4
5 Serial Nature There is one bus used to transport data and instructions Only One Instruction at a Time
6 Think about how programs are written in sequences….. . Instructions are stored in CPU registers .Locations are directly modified as a result of instruction execution Fetch Decode Execute Why Von Neumann Architecture? These sequences of instructions relate to the serial nature of Von Neumann processors.
Registers: 1- P rogram C ounter => PC 2- M emory A ddress R egister => MAR 3- M emory D ata R egister => MDR 4- C urrent I nstruction R egister => CIR 5- Acc umulator => ACC Other Important Components: 1- A rithmetic and L ogic U nit => ALU 2 - C ontrol U nit => CU 3-Buses 7
Processor Arithmetic & Logic Unit Control Unit PC MAR MDR CIR ACC Primary Memory Fetch Decode Execute Start Start Start Stop Stop Stop Copy address from PC to MAR Get data from primary memory and copy to MDR Copy from MDR to CIR Increment PC Split opcode from data (address) in MDR Control unit interprets opcode (Data) Address copied from CIR to MAR Get data from primary memory and copy to MDR Instruction executed 8 +1
Decode: Splitting an instruction Opcode Operand Opcode Operand 1 Operand 2 bit-15 bit-15 bit 0 bit Instruction Data or Address Result stored in A ccumulator 9
Executing instructions: . Calculations: - Contents of MDR sent to MDR . Jump Instructions: - Contents of MDR sent to PC 10