WAFER FABRICATION INTRODUCTION FOR PG STUDENTS

WAFER FABRICATION INTRODUCTION

1. Silicon crystal structure and defects. Czochralski single crystal growth. Growth rate and dopant incorporation for CZ method. Silicon shaping. Wafer preparation. Crystal growth, wafer fabrication and basic properties of silicon wafers 1

2. Why Silicon Silicon is the most important semiconductor for the microelectronics industry. When compared to germanium, silicon excels for the following reasons: (1) Si has a larger bandgap (1.1 eV for Si versus 0.66 eV for Ge). (2) Si devices can operate at a higher temperature (150 o C vs 100 o C). (3) Intrinsic resistivity is higher (2.3 x 10 5 Ω-cm vs 47 Ω-cm). (4) SiO 2 is more stable than GeO 2 which is also water soluble. (5) Si is less costly. 2

3. Sand to Silicon The sand that is used to produce silicon wafers is compose of mainly silicon dioxide. This can be made to react with carbon at very high temperatures. The silicon oxygen bond is very strong so a very high temperature process is needed for this carbon reducing reaction. The carbon replaces silicon to form silicon and carbon monoxide and carbon dioxide. This process is carried out in sub-merged electrode arc furnace. 3

4. Single crystal silicon Three types of solids - amorphous, polycrystalline, mono-crystalline (single-crystal). Semiconductor devices and VLSI (very large scale integrated) circuits require high-purity single-crystal semiconductors. Because: Difficult to control properties of amorphous or poly-crystals. By doping, electronic properties (carrier density, mobility, conductivity, carrier lifetime) of a single crystal can be controlled more precisely. Amorphous silicon is used in photovoltaic cells, electronic displays (large-area). Polycrystalline silicon is used as a gate contact in MOSFETs (VLSI circuits). Single crystal Si wafers Diameters: currently up to 300mm (500mm) Wafer thickness:  650 μ m Wafer purity: 150 parts/trillion Impurities: 99.99999999% Si 4

5. Microstructure of electronic materials SiO 2 gate oxide Polycrystalline materials 5

6. Raw material preparation 6

7. Economical value 7

8. Metallurgical Grade Silicon 8 This process generates polycrystalline silicon with about 98% to 99% purity and is called “ crude silicon” or “metallurgical grade silicon” (MGS). Crude silicon has a very high impurity concentration and so needs further refining for use in the semiconductor industry.

9. Production of MGS Silicon 9 Submerged electrode arc furnace is a power intensive process 13kWh/kg . Used to produce metal alloys. Purity 98 %. MGS-major impurities are B and C

10. 10

11. Production of EGS Silicon -Requires doping element ~ppb, C< 2ppm 11 Purification of silicon has several steps. First the crude silicon is ground into a fine powder. The powder is then fed into a reactor along with HCL vapour. At ~300 ºC trichlorosilane (TCS, SiHCL 3 ) is produced. This TCS vapour is then put through a series of filters, condensers and purifiers to produce ultra high purity TCS liquid. At high temperature TCS can react with hydrogen to produce high purity polysilicon. This high purity polysilicon is called Electronics Grade Silicon (EGS) and is ready for processing into a single crystal ingot.

12. CVD Reactor for EGS 12 Temp-1100˚C

13. Si reactor chlorosilane chemistry: SiCl 4 (gas)+H 2 (gas)  SiHCl 3 (gas)+ HCl (gas) SiHCl 3 (gas)+H 2 (gas)  SiH 2 Cl 2 (gas)+ HCl (gas) SiH 2 Cl 2 (gas)  SiCl 2 (gas)+H 2 (gas) SiHCl 3 (gas)  SiCl 2 (gas)+ HCl (gas) SiCl 2 (gas)+H 2 (gas)  Si(solid)+2HCl(gas) For silane it is not reversible: SiH 4 Si(solid)+2H 2 (gas) 13

14. Crystals are characterized by a unit cell which repeats in the x , y, z directions. Crystallography - introduction Planes and directions are defined using an x, y, z coordinate system . [ 111] direction is defined by a vector having components of 1 unit in x, y and z . Planes are defined by Miller indices - reciprocals of the intercepts of the plane with the x, y and z axes. For the (110) plane, it has intercepts with x, y, z-axis of 1, 1,  (i.e. no intercept with z-axis). So its Miller indices are (1/1, 1/1, 1/)=(1,1,0). For any plane (l, m, n), it is always perpendicular to the direction [l, m, n]. E.g. [111] direction is perpendicular to (111) plane. 14

15. Body-Centered Cubic (BCC) structure e.g. iron, chromium, tungsten, niobium

16. Face-Centered Cubic (FCC) structure e.g.: aluminum, copper, gold, silver

17. Diamond Cubic (FCC) structure

18. Zincblende structure Diamond structure, Zincblende structure e.g.: aluminum, GaAs e.g.: Si, Ge

19. Diamond Structure of Si Silicon has the basic diamond crystal structure: Two merged FCC cells offset by a/4 in x, y and z . 19

20. Point defects: vacancy, interstitial, substitutional, Frenkel defects Linear defects: edge and screw dislocations Planar defects: stacking fault, grain boundaries, surfaces Bulk defects: cracks and pores, precipitate Defect in crystals 20 A Frenkel defect is a type of point defect in crystalline solids named after its discoverer Yakov Frenkel . The defect forms when an atom or smaller ion leaves its place in the lattice, creating a vacancy, and becomes an interstitial by lodging in a nearby location.

21. Point defects Point defects . Substitutional. Interstitial. Vacancy (Schottky defect). Frenkel -type defect (interstitial - vacancy pair). Point defects dictate most dopant diffusion mechanisms, and thus determine the impurity profile. 21

22. The number of neutral vacancies is thermodynamically determined by, where N o is the density of atoms/cm 3 and E a is the activation energy for the formation of the vacancy (in silicon, N o =5.02 10 22 /cm 3 and E a =2.6 eV ) Point defects: vacancies and substitutional Substitutional can be foreign unwanted impurities, or intentionally introduced impurities. You may want a dopant impurity to be on a substitutional site, but you may not want a heavy metal atom or other unwanted impurity to be on a substitutional site (harder to remove). 22

23. Interstitials can be foreign unwanted impurities, intentionally introduced impurities, or “misplaced” host atoms (an intrinsic defect, the self-interstitial). Dopant atoms diffuse through the semiconductor faster as interstitials, but we need to place them in substitutional sites to make use of them (i.e. they act as dopants only when in substitutional sites). Point defects: interstitial Energies involved for the atomic diffusion of interstitial impurities 23

24. A missing line or additional line of atoms is called a dislocation. Dislocations are either pure edge, pure screw or a combination of both types. Line defects: dislocation Screw dislocations give a helical structure to the planes, often show up in crystal growth 24

25. Dislocation affects deformation properties - to slide upper block over lower now only requires a line of bonds to break at a time, not a whole plane process of slip. It causes low yield strength of solids. Dislocation sources: by stress due to temperature gradient, due to agglomeration. Dislocation move 25

26. A stacking fault is a disruption in the stacking of layers in the crystal. It is terminated by dislocation. Planar defects: stacking faults Volume defects: precipitates Precipitates are three dimensional defects that have a different chemical makeup from the host lattice. They can result from an impurity exceeding the maximum solubility of the crystal (much like super-saturation of sugar in water). 26

27. Crystal Growth 27 Two things are necessary to turn the EGS into a single crystal ingot, these are: High Temperature Single Crystal Silicon Seed With these two items, molten silicon is produced that can be made to condense with the same crystal structure as the seed silicon. There are two methods commonly used to produce single crystal silicon: The Czochralski Method (CZ) The Floating Zone method (FZ) Since only the CZ method can be used to make wafers with diameter greater than 200mm and it is a relatively low cost process, it is the most popular production method.

28. Jan Czochralski ( cho -HRAL- skee ) (1885 - 1953) was a Polish chemist who invented the Czochralski process, which is used to grow single crystals and is used in the production of semiconductor wafers. He discovered the Czochralski method in 1916 when he accidentally dipped his pen into a crucible of molten tin rather than his inkwell. He immediately pulled his pen out to discover that a thin thread of solidified metal was hanging from the nib. The nib was replaced by a capillary, and Czochralski verified that the crystallized metal was a single crystal. Si single crystal growth Two methods used: Czochralski (CZ) and float zone (FZ). 28

29. Czochralski method (CZ) It is widely employed for Si, GaAs , and InP . The EGS is broken into small pieces and placed in an SiO 2 crucible. In an argon ambient, the crucible is heated to just above 1417 o C. Dopant is added to the melt to intentionally dope the resulting crystal. A single crystal seed is then lowered into the melt (crystal orientation and wafer diameter determined by seed orientation and pull rate ), and withdrawn slowly. Melt flows up the seed and cools as crystal begins to grow. Seed rotated about its axis to produce a circular cross-section crystal. The rotation inhibits the natural tendency of the crystal to grow along certain orientations to produce a faceted crystal. Long ingots ( boules )  100 kg, with very good circular cross-section are produced. The oxygen and carbon (from graphite furnace components), contribute about 10 17 -10 18 /cm 3 contaminants. 29

30. Czochralski method (CZ) 30

31. Czochralski (CZ) crystal growing 31 Here the high purity EGS is melted in a slowly rotating quartz crucible at 1415 ºC (just above the melting point of silicon 1414ºC). A single crystal silicon seed rod is then mounted on a slowly rotating chuck and lowered into the molten silicon. The surface of the crystal begins to melt when it is submerged, however the seed crystal temperature is precisely controlled to be just below that of molten silicon. When the system reaches thermal stability the seed crystal is withdrawn very slowly, dragging some molten silicon to recondense around it (with the same crystal orientation).

32. The surface tension between the seed and the molten silicon causes a small amount of the liquid to rise with the seed and cool into a single crystalline ingot with the same orientation as the seed. The ingot diameter is determined by a combination of temperature and extraction speed. 32

33. A commercial CZ puller Early in the growth process Later in the growth process Czochralski growth of silicon 33

34. Silicon Ingot Grown by CZ Method 34

35. (1) Czochralski process - crystal growth rate Freezing occurs between isotherms X 1 and X 2 . latent heat of fusion (i.e . crystalization ) + heat conducted from melt to crystal (A) heat radiated away (C). heat conducted through the crystal (B) = = (A) (B) We wish to find a relationship between pull rate and crystal diameter. Heat balance: A 1,2 = Cross-sectional area 35

36. The rate of growth of the crystal is where v P is the pull rate and N is the density. Neglecting the middle term in Eqn. (1) we have: (2) (3) In order to replace dT /dx 2 , we need to consider the heat transfer processes. Heat radiation from the crystal (C) is given by the Stefan-Boltzmann law*: Heat conduction up the crystal is given by (4) (5) Czochralski process - crystal growth rate 2π rdx = radiation surface. σ = Boltzman constant k S = thermal conductivity of the solid. =1 for perfect blackbody. <1 for “grey-body”. 36

37. • Differentiating (5), we have (6) • Substituting (6) into (4), we have (7) • k S varies roughly as 1/T, so if k M is the thermal conductivity at the melting point, (8) (9) • Solving this differential equation, evaluating it at x = 0 and substituting the result into (3), we obtain (see text): (10) Czochralski process - crystal growth rate V pmax = maximum pull rate, inversely proportional to the square root of crystal radius. 37

38. Dopant incorporation during crystal growth Dopants are added to the melt to provide a controlled N or P doping level in the wafers. However , the dopant incorporation process is complicated by dopant segregation. Generally, impurities “prefer to stay in the liquid” as opposed to being incorporated into the solid. This process is known as segregation. The degree of segregation is characterized by the segregation coefficient, k o , for the impurity. C S C L C S and C L are the impurity concentration just on the either side of the solid/liquid interface. 38

39. Most k values are <1 which means the impurity prefers to stay in the liquid. Thus as the crystal is pulled, dopant concentration will increase . In other words, the distribution of dopant along the ingot will be graded. Dopant behavior during crystal growth 39

40. Steps for wafer preparation 40

41. Ingot Grinding / Flats making 41 The ingot is then ground down to the correct diameter to ensure a uniform surface and notched along one side. This notch will be used to determine the wafer orientation when it is being processed later on in the fab. Flat grind Diameter grind Notched grind

42. Traditional method of slicing Wire saw for large wafers Wafer slicing The saw blade itself is about 400 m thick, together with the loss at the seed and tail end of the crystal, only 50% of the boule ends up in wafer form. After slicing, mechanical lapping and wet chemical etching is performed before final chemical mechanical polishing. The wet etching is typically: 3Si + 4HNO 3 + 18HF  3H 2 SiF 6 + 4NO + 8H 2 O 42

43. Wafer Lapping 43 After the sawing processing the wafer edges are ground in a mechanical process to round the sharp edges created through the slicing process. The round edges prevent chipping of the wafers in later processes. After edge rounding the wafers are then rough polished to remove most of the damage caused by the wafer sawing process. This is known as lapping and is a double sided process performed under pressure using a glycerine slurry with alumina (Al 2 O 3 ) particles suspended in it. The lapping process removes about 50 μ m of silicon from both sides of the wafers but gives a flatness of ~2 μ m across the wafer.

44. Wafer Etch/Clean 44 After Sawing and Lapping the wafers are etched in a solution of nitric, hydrofluoric and acetic acid. The nitric acid oxides the silicon to form silicon dioxide on the surface of the wafer, which the HF then dissolves and removes. The acetic acid helps to control the reaction rate. This etch of the wafer surface removes about 10 μ m of silicon from both sides of the wafer, but it helps to further smooth the surface of the wafer while removing particles and defects from the wafers.

45. Wafer Polishing 45 A process called chemical mechanical polishing (CMP) is performed on the wafers to improve their planarity and ensure that all the wafers are of the same thickness. Here the wafer is held in a rotating holder and pressed onto a rotating polishing pad. Slurry and water are added to create an abrasive medium which slowly and evenly grinds and smoothes down the surface of the wafer. The slurry used is typically silica particles in a sodium hydroxide solution ( NaOH ). The particles have diameters of less than 100 Å so that scratches and gouges are not an issue. After polishing the wafers are cleaned using a mixture of HCL, H 2 O 2 and H 2 SO 4 to ensure the surface is contaminant free.

46. Chemical mechanical polishing The rotation and pressure generates heat that drives a chemical reaction in which OH - radicals from the NaOH oxidize the silicon. The SiO 2 particles abrade the oxide away. Slurry consists of nano-particles (10nm SiO 2 or Al 2 O 3 ) and chemicals ( NaOH ). 46

47. Common (not always) wafer surface orientation {100} wafer usually breaks along {110} plane (actually Si cleaves naturally along {111} plane, which meet the surface at an angle of 54.7 o , the angle between <001> and <111>). Sometimes (not often) {100} wafers break along {100} plane. ({100} = (100)+(010)+(001)) Another flat configuration for {100} n-type wafer Should be { 110 } plane 47

48. Wafer Cleaning Most wafer manufacturers use a 3-step process which starts with an SC1 solution (ammonia, hydrogen peroxide and RO/DI water ) to remove organic impurities and particles from the wafer surface. Next, natural oxides and metal impurities are removed with hydrofluoric acid. Finally, the SC2 solution, ( hydrofluoric acid and hydrogen peroxide), causes super clean new natural oxides to grow on the surface. 48

49. Reduction of Impurities that Effect Device Performance: 49 Reduce Contamination from environment 2. Wafer Cleaning 3. Gettering : -try to trap impurities away from device layers – process by which metal impurities in the device region are reduced by localizing them in predetermined, passive regions of the silicon wafer. ( phosphosilicate glass)

50. Gettering Strategies 50