2.Execution of Complete Instruction.pptx

The complete execution of an instruction involves the fetch-decode-execute cycle, where the processor first fetches the instruction from memory using the program counter (PC), then decodes it to understand the operation and required data, and finally executes the instruction by performing the specified action, such as arithmetic/logic operations or data transfers, before fetching the next instruction.

1. SNS COLLEGE OF TECHNOLOGY An Autonomous Institution Coimbatore-35 Department of Computer Science & Engineering 23ITT202 – Computer Organization & Architecture II B.E CSE / III SEMESTER UNIT III : Processor & Pipelining Topic 1 : Fundamental concepts

2. Let’s Recall !! 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT Register Transfer Notation (RTN) describes the transfer from one location in computer to another . Possible locations: memory locations, processor registers 2 /21 R2 ← [LOC]

3. Topics for discussion Instruction Execution Execution of Complete Instruction 07-10-2025 3 /21 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

4. Brai nStorm !! 07-10-2025 4/21 Guess 2.What is Execution? What is Instruction? COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

5. The CPU's Kitchen: A Recipe for Understanding Computer Organization 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 5 /21 Scenario: Optimizing a Smart Recipe Preparation System You are designing an AI cooking assistant that can prepare recipes autonomously. The system must handle recipe processing, ingredient management, and cooking execution. Analyze the Scenarios from Human and CPU perspective

6. Instruction Execution (1/3) 1) Fetch Phase –  2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR  PC [[PC]] [PC]+4 •Fetch the contents of the memory location pointed toby PC, andload into IR •Incrementthecontents of PC by 4. –Why 4?Instruction is32 bits (4B) and memory is byte addressable. CSCI2510 Lec10: Basic Processing Unit lines 16 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

7. Instruction Execution (2/3) 1) Fetch Phase –  2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR  PC [[PC]] [PC]+4 •Fetch the contents of the memory location pointed toby PC, andload into IR •Incrementthecontents of PC by 4. –Why 4?Instruction is32 bits (4B) and memory is byte addressable. CSCI2510 Lec10: Basic Processing Unit lines 17 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

8. Instruction Execution (3/3) 1) Fetch Phase –  2)Execute Phase – –Decode instruction in IR –Perform the operation(s) IR  PC PC+4 [[PC]] •Fetch the contents of the memory location pointed toby PC, and load into IR •Incrementthe contents of PC by 4. –Why 4?Instruction is32 bits (4B) and memory is byte addressable. CSCI2510 Lec10: Basic Processing Unit lines 18 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

9. Instruction Execution: Execute Phase •Aninstruction canbe executedby performing oneor more of the following operation(s): 1)Transfer data from a register to another register or to the ALU 2)Perform arithmetic (or logic) operations and store the result into the special register Z 3)Load content of a memory location to a register 4)Store content of a register to a memory location • Sequence of Control Steps : Describes how these operations are performed in processor step by step. CSCI2510 Lec10: Basic Processing Unit 19

10. 1) Register Transfer • Inputandoutput of register Riare controlled by switches ( ): –Ri-in :Allow datatobe transferred intoRi –Ri-out :Allow data to be transferred out fromRi CSCI2510 Lec10: Basic Processing Unit lines 20 Ri Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … Ri-in Ri-out

11. 1) Register Transfer (Cont’d)  •Ex:   R1-out, R3-in •Recall: R3 [R1] Sequence of Steps:  Clock 2: •Reset R1-out to 0 •Reset R3-in to 0 Clock Cycle C lock Clock 1:R1-out, R3-in •Set R1-out to 1 •Set R3-in to 1 •Set allothers to 0 Note:Onlystate“sets”forshort. CSCI2510Lec10:BasicProcessingUnit lines 21 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

12. Class Exercise 10.1 •Whatis the sequence of steps for the following operation?  R1 [R3] CSCI2510 Lec10: Basic Processing Unit lines 22 Student ID: Name: Date: Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

13. CSCI2510 Lec10: Basic Processing Unit lines 24 2) Arithmetic or Logic Operation Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internalprocessor bus Control signals … Select XOR Carry in n-1 … … R1-out, Y-in Select-Y, R2-out, B-in, Add, Z-in Z-out, R3-in • ALU :A circuitwithout storage to manipulate data. – : #4or registerY Sequence of Steps: – – :fromA&B : Perform operation R3 : to register Z  Two inputs ALU One output • • : Any otherregister A B •Ex: [R1] + [R2]   

14.    R1-out, Y-in Select-Y R2-out, B-in, Add , Z-in Z-out, R3-in CSCI2510 Lec10: Basic Processing Unit 25 2) Arithmetic or Logic Operation (Cont’d)  •Ex: R3 [R1]+ [R2]

15. Class Exercise 10.2 •Whatis the sequence of steps for the following operation?  R6 [R4] – [R5] CSCI2510 Lec10: Basic Processing Unit lines 26 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

16. Recall: Processor-Memory Interface • Data transferring takesplace through M A R andM D R. – – : Memory Address Register : Memory Data Register MAR MDR CSCI2510 Lec06: Memory Hierarchy 28 M D R Control lines ( R / W , MFC, etc.) k -bit address bus (byte-addressable) n -bit Up to 2k addressable memory locations Word length = n bits Processor M A R Memory data bus (unit: word ) *MFC(MemoryFunction Completed): Indicating the requested operation has been completed.

17. Recall: Assembly-Language Notation •Assembly-Language Notation isusedtorepresent machine instructions and programs. –An instructionmust specifyan operation to beperformed and the operands involved. – Ex. The instruction that causes the transfer from memory location LOC to register R2: –Sometimes operations are defined by using mnemonics . Load R2, LOC Load : operation; Load LOC R2 ST . 29 : sourceoperand; : destination operand. • • E.g. : abbreviations ofthewordsdescribingoperations can be written as LD , Store can be written as STR or Mnemonics CSCI2510 Lec04: Machine Instructions Some machines may put destination last : operation src, dest

18. CSCI2510 Lec10: Basic Processing Unit 30 3) Loading Word from Memory MDR-inE MDR-outE MAR MDR MDR-in MDR-out MAR-in E xternal memory bus ( data lines ) E xternal memory bus ( address lines ) Internal processorbus Register • MAR :MemoryAddress Register  – Uni-directional bus( ) –Connect to the address lines directly –Bi-directionalbus ( –MDR connections to ) buses are all controlled by switches ( ).  :Memory Data • MDR

19. WaitMFC •Ex:  R1-out, MAR-in, Read MDR-out, R2-in MovR2, (R1) Sequenceof Steps:  (start to load a word from memory) (wait until the loading is completed)  MDR-inE, CSCI2510Lec10:BasicProcessing Unit 31 Z PC R/W MFC (Control lines) MAR Addr lines MDR Data lines Y Constant 4 MUX Add Sub A B ALU R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … 3) Loading Word from Memory (Cont’d)

20. Timing Sequence: ,  R1-out (not shown) MAR-in, Read (start to read a word from memory) === assume memory read takes 3 cycles ===  MDR-inE, WaitMFC (wait until the loading is completed) MDR-out, R2-in (not shown)  CSCI2510Lec10:BasicProcessingUnit 32 3) Loading Word from Memory (Cont’d) • 1 2 3 Cycle 5 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Data Memory Read (MR) Data bits Address bits appear on Address Bus (MAR content) MDR MDR MAR MFC Clock Step Read Address inE in out

21. Class Exercise 10.3 •Whatis the sequence of steps for the following operation? Mov R4,(R3) CSCI2510 Lec10: Basic Processing Unit lines 33 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

22. CSCI2510 Lec10: Basic Processing Unit 35 4) Storing Word to Memory Select XOR Carry in Z PC R/W MFC (Control lines) MAR Addr lines MDR Data lines Y Constant 4 MUX Add Sub A B ALU R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … … Write MDR-outE, WaitMFC •This operation issimilar to the previous one. •Ex: Mov(R1), R2 Sequence of Steps:  R1-out, MAR-in   R2-out,MDR-in, (starttostorea word into memory) (wait until the storing is completed)

23. Class Exercise 10.4 •Whatis the sequence of steps for the following operation? Mov (R3), R4 CSCI2510 Lec10: Basic Processing Unit lines 36 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … …

24. Loading Word vs Storing Word CSCI2510 Lec10: Basic Processing Unit 38 R2-in • •Ex:  R1-out, MAR-in, Read MDR-inE , WaitMFC • •Ex:  R1-out, MAR-in  R2-out, , , WaitMFC MDR-out , Loading Word MovR2, (R1) Write MDR-outE Storing Word Mov(R1), R2    MDR-in

25. Revisit: Fetch Phase of stepsfor the fetch phase with the highest parallelism? • FetchPhase :The firstphase of machine instruction execution –  CSCI2510Lec10:Basic ProcessingUnit lines 39 Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … IR [[PC]] •Increment the contents of PC by 4 •Fetch the instruction from the memory location pointed to by PC, and load it into IR  – PC [PC]+4 • Whatis thesequences

26. Fetch Phase (1/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in •Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Increment PC – Y-in is for branch –Fetchthe instruction in parallel (discuss later). CSCI2510Lec10:Basic ProcessingUnit 40 Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … …

27. Fetch Phase (2/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in •Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Y-inisfor branch (discuss later). –Fetchthe instruction –Increment PCinparallel. CSCI2510Lec10:Basic ProcessingUnit 41 Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … …

28. Fetch Phase (3/3) MDR-out, IR-in MDR-inE, WaitMFC Z-out, PC-in, Y-in •Ex: Fetch Phase Sequence of Steps:  PC-out, MAR-in, Read Select-4, B-in, Z-in, Add   –Y-inisfor branch (discuss later). –Fetchthe instruction –Increment PCinparallel. CSCI2510Lec10:Basic ProcessingUnit 42 Select XOR Carry in Z Y Constant 4 MUX Add Sub A ALU B PC R/W MFC (Control lines) MAR Addr lines MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic n-1 ALU control lines External memory bus Internal processor bus Control signals … … …

29. Observations and Insights •Independent operations imply the possibility of performing some steps in parallel . •During memory access, processor waits for MFC . •The internal processorbus andthe external memory bus can be operated independently (concurrently). – Since the separation provided by MAR and MDR. – E.g.,memory access and PC increment, instruction – There is NOTHING TO DO BUT WAIT for few cycles. – decoding and reading source register Question: Any way to improve this situation? CSCI2510 Lec10: Basic Processing Unit 43

30. Processing Clock Speed   :  How fast you chop (GHz = chops per second) Cores   :  How many hands you have (more cores = can chop and stir simultaneously) Cache Size  :  How big your cutting board is (more space for immediate work) Bottlenecks Slow Storage  : Walking far to pantry each time Insufficient RAM   :  Small counter, constantly cleaning space Slow CPU  :  Careful, methodical chopping Thermal Throttling   :  Kitchen getting too hot, slowing down 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 30 /21

31. Lets Explore !! Basic Processing Unit: Processor • Executes machine-language instructions . • Coordinates other units • central processing unit (CPU) . – The term “central” is no longer appropriate today . – Today’s computers often include several processing units. • E.g.,multi -core processor, graphic processing unit (GPU),etc. COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 07-10-2025 7/21

32. U nderstanding of process and data flow Arithmetic and Logic Unit (ALU) Register file : a memory unit for the processor’s general- purpose registers (GPRs) Instruction address generator PC Register file IR Control circuitry : Perform anarithmetic orlogic operation Processor-memory interface : Allow the communication between processor and memory Control circuitry : Interpret or decode the fetched instruction IR : Hold the instruction until its execution is completed ( PC : Keep track of the address of the next instruction to be fetched and executed ( special purpose register ) special purpose register ) ALU Processor–memory interface DT-E mpathize 8/21 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 07-10-2025

33. Processor Internal Bus (1/2) • lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … Internal Processor Bus: –ALU, control circuitry , and all the registers are interconnected via a single common bus . DT-Define COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 9/21 07-10-2025

34. Processor Internal Bus (2/2) • lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … • External Memory Bus: Internal Processor Bus: – – parts: data path parts: control path – Brown part: external memory path( NOT internal processor bus!) – The common bus is Internal to the processor. • i.e.only visible to the processor. Black Blue COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 10/21 07-10-2025

35. Processor Internal: External Bus (1/2) • lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External output memory bus input Internalprocessor bus Control signals … Select XOR Carry in n-1 … … External Memory Bus : – : External memory bus are controlled through MAR and MDR. – MAR : Specify the requested memory address Processor-memory interface • Input : Address is specified by processor via internal processor bus. • Output : Address is send to the memory via external memory bus . COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 11/21 07-10-2025

36. Processor Internal: External Bus (2/2) • lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus two outputs two inputs Internalprocessor bus Control signals … Select XOR Carry in n-1 … … External MemoryBus: – MDR : Keep the content of the requested memory address • Outputs : Data stored in MDR may be loaded from either bus. •There are two inputs and two outputs for MDR. • Inputs : Data may be placed into MDR either –From the internal processor bus or –From the external memory bus . COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 12/21 07-10-2025

37. Processor Internal: Register (1/2) • lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internalprocessor bus Control signals … Select XOR Carry in n-1 … n-1 … • General-Purpose Registers: Special Registers: – – – R through R n • variesfrom one processor to another. •Hold the instruction until the current execution is completed. of the next instruction to be fetched and executed. Program Counter Instruction Register • Keep track of the address 13/21 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

38. Processor Internal: Register • Special Registers: Y, Z, & TEMP – Transparent to the programmer. – Used by the processor for temporary storage during execution of some instructions. – Never used for storing data generated by one instruction for later use by another instruction. lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internal processor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 14/21 07-10-2025

39. Processor Internal: Control Circuitry • • Control logic : Instruction decoder : –Interact with the external memory bus . –Issue control signals to control the all the units inside the processor. –Interpretthefetched instruction stored in the IR register. •E.g., ALU control lines, select signal for MUX, carry-in for ALU, etc. lines Address lines Data Z PC Y Constant 4 MUX Add Sub A ALU MAR MDR B R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus Internalprocessor bus Control signals … Select XOR Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 15/21 07-10-2025

40. Processor Internal: Internal Bus • Unit (ALU) : Arithmetic and Logic –The Select ( – Perform arithmetic or logic operation Z = A operator B A B of ALU: ) either input A •Two inputs •One output to register • The output of register Y or •A constant value 4 (for incrementing PC). Z • Multiplexer(MUX) : ctrl line lines Address lines Data Y Constant 4 MUX Z PC ALU MAR MDR R IR R0 R1 R2 R3 TEMP Instruction decoder & control logic ALU control lines External memory bus A B Internalprocessor bus Control signals … Select XOR Add Sub Carry in n-1 … … COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 16/21 07-10-2025

41. Let’s summarize 07-10-2025 41 /21 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

42. 07-10-2025 Shall We Break for Tea! Team Activity Design a "Smart Tea Maker" using computer architecture principles Take a minute to think about it, then discuss within your team and devise the model /solution Consider: what components is required ? Hint: Revisit on the process and Flow of components 42 /21 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

43. Assessment- Quiz Human Brain Functions Computer Components Remembering tea recipe RAM (Memory ) Answer Current step in mind Storage (HDD/SSD) Decision to add sugar ALU Tasting and checking Control Unit Muscle memory stirring I/O Devices Seeing the tea color Cache Memory 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT 43 /21 1. Match the Components (Draw lines to connect) Remembering tea recipe → Storage Current step in mind → RAM Decision to add sugar → Control Unit Tasting and checking → I/O Devices Muscle memory stirring → ALU Seeing the tea color → I/O Devices

44. References Carl Hamacher , Zvonko Vranesic and Safwat Zaky ,“Computer Organization”, McGraw-Hill,5th Edition 2014. https ://archive.nptel.ac.in/courses/106/105/106105163 / 07-10-2025 44 /21 07-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT

45. 07-10-2025 45 /21 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT