A case study on Data Memory Access. - DMA - DMA Controller -Working Mechanism - Modes of Transfer

A case study on Data Memory Access.
- DMA
- DMA Controller
-Working Mechanism
- Modes of Transfer

1. Data Memory Access (DMA) A Case Study on By: Prajal Gurung Suyan Thapa

2. Background Traditionally, data transfer between memory and peripherals (such as disks, network cards, or audio devices) is managed by the CPU. T ime Consuming CPU Memory I/O Device 1 st cycle 2nd cycle

3. So, in order to save time ,here DMA comes in existence DMA (Data Memory Access) is a method that allows Input/Output device to send or receive data directly to or from Memory without the involvement of CPU. Direct Memory Access  uses hardware for accessing the memory, that hardware is called a DMA Controller .  CPU Memory I/O Device Directly access

4. CPU I/O Device Memory DMAC Starting Address Data Count 1. DMA Req 2. HOLD 4. HLDA System Bus 6. 2. HOLD 3. 1. DMA Req 5. DMA Ack Fig: Working of DMA controller

5. Starting Address : Memory Address, starting from where data transfer should be performed. Data Count : No of bytes or words to be transferred. Initially After 1B After 2B After 3B 1000 1001 1002 1003 500 499 498 497 Starting Address Data Count Data Count: 497---496—495--------------3—2—1—0 ( Stops ) Data Transfer completed Working of DMA controller

6. Working of DMA controller During DMA transfer, CPU can perform only those operations which donot require System Bus which means mostly CPU will be blocked. Whenever control is given to DMAC then donot give it for a longer time .

7. Modes of Transfer Burst Mode : In burst mode, the DMA controller transfers a block of data in one continuous burst. During this time, the DMA controller takes control of the system bus and transfers data continuously until the entire block is moved. This mode is efficient for large data transfers but can temporarily block the CPU and other devices from accessing the bus.

8. Modes of Transfer Cycle Stealing Mode : Slow IO device will take some time to prepare data (or word) and within that time CPU keeps the control of the buses. Once the data or the word is ready CPU give back control of system buses to DMAC for 1-cycle in which the prepared word is transferred to memory. This mode is efficient for large data transfers but can temporarily block the CPU and other devices from accessing the bus.

9. Modes of Transfer InterLeaving Mode : Whenever CPU does not require the system buses then only control of buses will be given to DMAC. In this mode, CPU will not be blocked due to DMA at all. This is the slowest mode of DMA Transfer since DMAC has to wait might be for so long time to just even get the access of system buses from the CPU itself. Hence due to which less amount of data will be transferred.