CE-221-wk10-L28L29L30-ashah. pdf

a

1. Encoders, Code Converters, Multiplexers (Data
Selectors), Demultiplexers, Parity Generators
/Checkers, Latches, Edge-Triggered Flip-Flops,
CE-221
Digital Logic Design
Lecture No L28L29L30
AcademicWeek No 10
[email protected]

2. Course contents: weekly breakdown
Introductory Concepts: digital and analog quantities, binary digits, logic levels,
and digital waveforms; basic, combinational, and sequential logic functions; as
well as programmable and fixed-function logic devices
wk01
Decimal Numbers, Binary Numbers, Decimal-to-Binary Conversion, Binary
Arithmetic, Complements of Binary Numbers,
wk02
Signed Numbers, Arithmetic Operations with Signed Numbers, Hexadecimal
Numbers, Octal Numbers, Binary Coded Decimal (BCD), and Digital Codes.
wk03
Error Detection and Correction Codes, The Inverter, The AND Gate, The OR
Gate, and The NAND Gate
wk04
The NOR Gate, Exclusive-OR, and Exclusive-NOR Gates, Boolean Operations
and Expressions, the Laws and Rules of Boolean Algebra.
wk05
DeMorgan'sTheorem, Boolean Analysis of Logic Circuits, simplification using
Boolean Algebra and standard forms of Boolean expressions, Boolean
Expressions and Truth Tables, and the Karnaugh Map
wk07
Karnaugh Map SOP & POS Minimization. Basic Combinational Logic Circuits,
Implementing Combinational Logic, The Universal Property of NAND and NOR
Gates, Combinational Logic Using NAND and NOR Gates, and Pulse
Waveform Operation.
wk08
Midweek

3. 3
Course contents: weekly breakdown
Basic Adders, Parallel Binary Adders, Ripple Carry versus Look-Ahead Carry
Adders Comparators, Decoders, Encoders, Code Converters
wk09
Multiplexers (Data Selectors), Demultiplexers, Parity Generators/Checkers,
Latches, Edge-Triggered Flip-Flops, Flip-Flop Operating Characteristics, Flip-
Flop Applications, Asynchronous Counter Operation
wk10
Synchronous Counter Operation,Up Down Synchronous Counters,Design of
Synchronous Counters,Cascaded Counters
wk11
Decade Counter CounterApplications,Logic Symbols with Dependency
Notation
wk12
Basic Shift Register FunctionsSerial In/Serial Out Shift RegistersSerial
In/Parallel Out Shift Registers
wk13
Parallel In/Serial Out Shift RegistersParallel In/Parallel Out Shift Registers
Bidirectional Shift Registers
wk14
Shift Register CountersShift Register ApplicationsBasic Memory Devices and
their Applications
wk15
Final

4. Encoder
•isacombinationallogiccircuitthatperformsthe
reverseofadecoderfunction.
•acceptsanactivelevelononeofitsinputs
(representingadigitorsymbol)andconvertsit
toacodedoutput(suchasBCDorbinary).
Theprocessofconvertingsymbolsornumbers
intoacodedformatiscalledencoding.
4

5. The Decimal-to-BCD Encoder
5

6. Basic logic diagram of a decimal-to-BCD
encoder
6

7. 7
Assembler as a Software
Encoder

8. The Decimal-to-BCD
Priority Encoder
•Performsthesamebasicencodingfunctionasa
regularencoder,butwithaddedflexibilityfor
prioritydetection.
•PriorityFunction:TheencoderproducesaBCD
outputforthehighest-orderactivedecimaldigit
input,ignoringlower-orderactiveinputs.
•Example:Ifinputs6and3areactive,theBCD
outputwillbe0110(representingdecimal6).
8

9. IMPLEMENTATION: DECIMAL-TO-BCD
ENCODER
9

10. The Decimal-to-BCD encoder
10

11. Code converters
are combinational circuits that convert data from one code to another
BCD-to-Binary Conversion
The binary numbers representing the weights of the BCD bits
are summed to produce the total binary number.
11

12. Code Converters
BCD-to-Binary Conversion
The BCD bits have weights of 80, 40, 20, 10 for
the tens digit and 8, 4, 2, 1 for the units digit,
12

13. 13

14. Binary-to-Gray
and Gray-to-Binary Conversion
•Exclusive-ORgatesconvertbinarytoGraycode
byprocessingeachbitcombination.
•Exclusive-ORgatesarealsousedtoconvert
Graycodebacktobinary.
•PLDscanbeconfiguredforbothbinary-to-Gray
andGray-to-binaryconversions.
14

15. 15
Four-bit binary-to-
Gray conversion logic.
Four-bit Gray-to binary
conversion logic.

16. Binary-to-Gray and Gray-to-Binary
Conversion
16

17. 17

18. 18

19. Multiplexers (Data Selectors)
•Amultiplexer(MUX)isacombinationalcircuitthat
selectsandroutesdatafrommultipleinputlinestoa
singleoutputlinebasedonaselectsignal.
•Itconsistsofmultipledatainputlines,asingle
outputline,andselectlinesthatcontrolwhichinput
isconnectedtotheoutput.
19
In a multiplexer,
data are
switched
from several
lines to one line.

20. 20

21. 21
For an n-input multiplexer,
there are 2^n possible
inputs and n selection lines.
2 data-select inputs4
inputs
Multiplexers are also
known as data
selectors.

22. 22
ORingcombines AND conditions to select the correct data input.

23. Logic diagram for a 4-input multiplexer
23

24. output waveform in relation to the inputs
24

25. 25
The 74HC153 dual four-input data selector/multiplexer.
Each multiplexer has its own active-low enable input (1E
and 2E) to control the output.
four input lines (I0-I3)

26. 26

27. EIGHT-INPUT DATA SELECTOR/MULTIPLEXER
27

28. A Logic Function Generator
application of MUX
28
Implement logic function with 74HC151 multiplexer,
compare gate implementation.

29. 29

30. Demultiplexer
•Ademultiplexerreversesmultiplexingbyrouting
datafromoneinputtomultipleoutputs.
•Itswitchesdatafromoneinputlinetotwoor
moredatalinesdependingontheselectinputs.
•Decoderscanfunctionasdemultiplexers,
performingasimilardata-routingtask.
30

31. 31

32. 32

33. 33
The select lines cycle through a binary sequence,
routing each input bit to D0–D3 in order.

34. 4-Line-to-16-Line Decoder as a Demultiplexer
•A4-line-to-16-linedecodercanalsobeusedas
ademultiplexer.
•Indemultiplexerapplications,theinputlines
functionasdata-selectlines,andonechipselect
inputservesasthedatainput.
•TheotherchipselectinputisheldLOWto
enabletheinternalnegative-ANDgate,as
showninthelogicsymbolinFigure6–54.
34

35. Parity Generators/Checkers
•Parity adds an extra bit to ensure the total
number of ones is even (even parity) or odd (odd
parity).
•Errors in digital systems can cause bit changes
(e.g., 1 to 0 or 0 to 1) during transfer.
•While single-bit errors are rare, undetected errors
can cause serious issues, making error detection
essential.
35

36. •Parityisdeterminedbysummingthe1sina
codeusingmodulo-2arithmetic.
•XORgatesareusedtosumbits,producing0for
evenparityand1foroddparity.
36

37. 37

38. 38

39. 39

40. Troubleshooting
•Aglitchisabrief,undesiredvoltagespikethat
cancauseimproperoperationinlogiccircuits.
•Glitchesindecoders,likethe74HC138,occur
duetotimingdelaysbetweeninputtransitions,
andcanbedetectedandeliminatedusinga
logicanalyzeroroscilloscopewithoutput
strobing.
40

41. 41

42. 42

43. Traffic Signal Controller -Key Concepts
application project
•Timing Requirements
•Main Street Green Light:
–Stays on for at least 25 seconds (or longer if no vehicle on the
side street).
•Side Street Green Light:
–Stays on until no vehicle is detected (up to 25 seconds).
•Yellow Light (Caution):
–On for 4 seconds on both streets when switching from green to
red.
43

44. 44

45. Simplified Flow of Traffic Signal System:
•Main street green → If no car on side street, wait
25s, otherwise detect vehicle and move to next
state.
•Yellow caution light → Both streets get 4s yellow
light.
•Side street green → If car present, stay green
for 25s, else go back to main street green.
45

46. •Combinational Logic: Controls signal lights and
triggers timers based on state inputs.
•Timing Circuits: Generates 25s and 4s timing
signals using a 1 Hz clock from the system
clock.
•Sequential Logic: Produces 2-bit Gray codes to
manage state transitions for the traffic lights.
46

47. 47

48. Chapter 7
•Thischapterintroducessequentiallogic
fundamentals,coveringbistable,monostable,and
astabledevicescalledmultivibrators.
•Bistabledevicesincludelatchesandflip-flops,which
havetwostablestates(SETandRESET)andare
usedasstoragedevices.
•Themonostablemultivibrator(one-shot)producesa
singlepulse,whiletheastablemultivibratorisused
asanoscillatorforgeneratingtimingwaveformsin
digitalsystems.
48

49. Sequential Logic Circuits
•Outputsdependonboth currentand
previousinputs.
•Can"remember"previousinputs,providing
memoryviafeedbackfromtheoutputto
theinput.
•Storedinformationisreferredtoasthe
state.
49

50. Combinational vs Sequential Logic
memoryand feedback

51. Sequential Logic Circuits
a sequential logic circuit is specified by a time
sequence of inputs, outputs, and internal states.
51
two main types of sequential logic circuits:
Asynchronous and Synchronous

52. Types of Sequential Logic Circuits
Asynchronous circuits
–Do not have a clock signal.
Synchronous circuits
–A clock signal is applied to the circuit.
–The clock signal is a periodic waveform with
frequency f.
–The circuit updates its output only on a clock edge.
–Can be positive-edgeor negative-edgetriggered.
52

53. 53
Sequential Circuits
Asynchronous
Combinational
Circuit
Memory
Elements
Inputs Outputs
Asynchronouscircuitslackaclocksignal:
Outputchangesimmediatelyinresponseto
inputchanges,independentofanyclocksignal.

54. Sequential Circuits
Synchronous
54
Combinational
Circuit
Flip-flops
Inputs Outputs
ClockSynchronous circuits use a clock signal

55. 55

56. Latches
Temporarilystoredatainmemorycircuits,holding
avalueuntilitisupdatedorchanged.
SRLatch: two cross-coupled NOR gates or two
cross-coupled NAND gates
56

57. 57
Latches
The latch has two useful states. When
Q = 1 and Q’= 0set state
Q = 0 and Q’= 1reset state

58. 58
Latches
•SRLatch
Q’QS R Q
0
0 0 0
0
1
0
0
10
Q= Q
0
Initial Value

59. 59
•SRLatch
Q’QS R Q
0
100 0 0
0 0 1
1
0
0
0
01
Q= Q
0
Q= Q
0
Latches

60. 60
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
00 1 0
0
1
1
0
1
Q= 0
Q= Q
0
Latches

61. 61
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
100 1 0
0 1 1
1
0
1
0
10
Q= 0
Q= Q
0
Q= 0
Latches

62. 62
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
100 1 0
100 1 1
1 0 0
0
1
0
1
01
Q= 0
Q= Q
0
Q= 1
Latches

63. 63
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
100 1 0
100 1 1
011 0 0
1 0 1
1
0
0
1
01
Q= 0
Q= Q
0
Q= 1
Q= 1
Latches

64. 64
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
100 1 0
100 1 1
011 0 0
011 0 1
1 1 0
0
1
1
1
00
Q= 0
Q= Q
0Q= 1
Q= Q’
0
Latches

65. 65
•SRLatch
Q’QS R Q
0
100 0 0
010 0 1
100 1 0
100 1 1
011 0 0
011 0 1
001 1 0
1 1 1
1
0
1
1
00
Q= 0
Q= Q
0Q= 1
Q= Q’
0
Q= Q’
Latches

66. 66
•SRLatch
QS R
Q
0
0 0
00 1
11 0
Q=Q’=01 1
No change
Reset
Set
Invalid
QS R
Q=Q’=10 0
10 1
01 0
Q
0
1 1
Invalid
Set
Reset
No change
Latches

67. 67
•SRLatch
QS R
Q
0
0 0
00 1
11 0
Q=Q’=01 1
No change
Reset
Set
Invalid
QS’ R’
Q=Q’=10 0
10 1
01 0
Q
0
1 1
Invalid
Set
Reset
No change
Latches

68. 68

69. 69

70. 70

71. VHDL description
71
Theinoutkeywordallowscross-couplingbetweenQ
andQNotoutputs,whilestd_logicrepresentssingle-
bitdigitallogicwithmultiplestatesformodeling
circuits.

72. Application
The Latch as a Contact-Bounce
Eliminator
72
S-R latcheliminates switch contact bounce, ensuring stable output.
Latch maintains clean transitions despite brief voltage spikes from
bounce.

73. 73
•SRLatch with Control Input
QC S R
Q
0
0 x x
Q
0
10 0
010 1
111 0
Q=Q’11 1
No change
No change
Reset
Set
Invalid
Controlled Latches
The Gated S-R Latch

74. 74

75. 75
Controlled Latches
•DLatch (D= Data)
QC D
Q
0
0 x
010
111
No change
Reset
Set
C
Timing Diagram
D
Q
t
Output change possible

76. Gated D-latch
Q follows D
76

77. Inputs
–D(DataInput):Thedatatobestoredinthelatch.
–ENorC(EnableInput):Controlsthelatchingaction.
WhenEishigh,thelatchisenabled,andtheinputDis
stored.WhenEislow,thelatchisdisabled,andthe
outputremainsunchanged.
Outputs
–Q:Themainoutput,whichholdsthestoreddata.
–Q'(Q-bar):ThecomplementoftheQoutput.
77
Gated D-latch
Q follows D

78. 78
Controlled Latches
•DLatch (D= Data)
QC D
Q
0
0 x
010
111
No change
Reset
Set
C
Timing Diagram
D
Q
Output change possible,
Q follows D

79. 79

80. IMPLEMENTATION: GATED D LATCH
80

81. 81

82. Flip-Flops and Multivibrators
The fundamental sequential logic component is a
flip-flop:
–It is a bi-stable multivibrator circuit.
–Bi-stable means it has two stable states.
–It can store a single bit (logic 0 or logic 1).
Other types of multivibrator circuits are astable
multivibrator, and mono-stable multivibrator.
82

83. •Astable Multivibrator
–Has zero stable states (e.g., oscillator).
–Continuously switches between two states without an
external trigger.
–Applications: Clock generation, timing circuits.
•Mono-stable Multivibrator
–Has one stable state and produces a single output
pulse when triggered.
–The circuit returns to its stable state after the pulse
duration.
–Used for generating time delays or single pulses (e.g.,
one-shot).

84. 84
Flip-Flopsareusedtostoreinformation,
whilemultivibratorsareusedtogenerate
timingsignalsorpulses.

85. 85
Flip-Flops
•Controlled latches are level-triggered
•Flip-Flops are edge-triggered
C
CLK Positive Edge
CLK Negative Edge

86. Flip-flops
•Flip-flopsaresynchronousbistable
devicesthatchangestateattheclock's
leadingortrailingedge,unlikelevel-
sensitivegatedlatches.
•DandJ-Kflip-flopscanbepositiveor
negativeedge-triggered,identifiedbya
triangleattheclockinputintheirlogic
symbols.
86

87. 87
Flip-Flops

88. 88

89. Operation of a positive edge-triggered
D flip-flop
89
Q follows D at the triggering edge of the clock.

90. DeterminetheQandQ’outputwaveformsoftheflip-flopin
Figure7–15fortheDandCLKinputsinFigure7–16(a).Assume
thatthepositiveedge-triggeredflip-flopisinitiallyRESET.
1. At clock pulse 1, D is LOW, so Q remains LOW (RESET).
2. At clock pulse 2, D is LOW, so Q remains LOW (RESET).
3. At clock pulse 3, D is HIGH, so Q goes HIGH (SET).
…

91. 91
Semiconductormemoriesconsist
ofcellsthatholda1or0.
SRAMusesflip-flopsforstorage
andretainsdataaslongaspower
issupplied,butisvolatile.
DRAMusescapacitancefor
storageandneedsperiodic
refreshingtomaintaindata.

92. •Threeoperationscanbeperformedwithaflip-
flop:setitto1,resetitto0,orcomplementits
output.
•TheDflip-flophasasingleinputandcansetor
resettheoutputbasedontheDinputvalue
beforetheclocktransition.
92

93. The J-K Flip-Flop
The JK flip-flop, synchronized by a clock signal and
having two inputs (J and K), can perform all three
operations: set, reset, or complement the output.
93

94. •WhenJ=1andK=0,D=Q+Q’=1,sothenext
clockedgesetstheoutputto1.
•WhenJ=0andK=1,D=0,sothenextclockedge
resetstheoutputto0.
•Whenboth J=K=1andD=Q’,thenextclock
edgecomplementstheoutput.Whenboth
•J=K=0andD=Q,theclockedgeleavesthe
outputunchanged.
94

95. The J-K Flip-Flop
TheJ-Kflip-flophassynchronousJandKinputs,
whichtransferdatatotheoutputonlyonthe
clock'striggeringedge.
operation of a positive edge-triggered flip-flop

96. 96
operation of a positive edge-triggered flip-flop
When J and K are HIGH, the
flip-flop toggles;
When both J and K are
LOW, the output does not
change from its prior state
the flip-flop cannot change state except on the triggering edge of a
clock pulse (positive in this case)

97. 97

98. Thewaveformsin(a)areappliedtotheJ,K,andclockinputsas
indicated.Determinethe Q output,assuming
thattheflip-flopisinitiallyRESET.
98
negative edge-triggered flip-flop

99. T (toggle) flip-flop
TheT(toggle)flip-flopisacomplementingflip-flop
andcanbeobtainedfroma JKflip-flopwhen
inputsJandKaretiedtogether
99

100. T (toggle) flip-flop
100

101. Given the waveforms in (a) for the D input and the
clock, determine the Q output waveform if the flip-
flop starts out RESET
101

102. Asynchronous Preset and Clear Inputs
•Fortheflipflops,theDandJ-Kinputsarecalled
synchronousinputs.
•Integratedcircuitflip-flopsoftenhave
asynchronousinputs(preset/clear)thatchange
thestateindependentlyoftheclock.
•Theseinputsaretypicallyactive-LOW,andfor
synchronousoperation,bothpresetandclear
mustbekeptHIGH.
102

103. 103

104. Forthepositiveedge-triggeredDflip-flopwithpreset
andclearinputsasshown,determinetheQoutputfor
theinputsshowninthetimingdiagraminpart(a)ifQis
initiallyLOW.
104

105. Edge-Triggered D Flip-Flop
105

106. Edge-Triggered D Flip-Flop
106

107. Level-SensitiveLatches:
Latchesarecalledlevel-sensitivebecause
theiroutputfollowstheirinputswhen
enabled,remainingtransparentwhilethe
enablesignalisactive.
Edge-TriggeredFlip-Flops:
Foroutputchangesonlyattherisingor
fallingedgeoftheenablesignal(usuallythe
clock),anedge-triggeredflip-flopisused.
107

108. D Flip-Flop Structure:
A positive-edge-triggered D flip-flop consists
of two D latches connected in series, with
the clock signal (Clk) controlling the enable
(E) inputs of each latch.
•Master Latch: The first latch, called the
master latch, is enabled when Clk= 0 and
follows the input D.
108

109. •SlaveLatch:Thesecondlatch,calledthe
slavelatch,isenabledwhenClk=1and
transfersthemasterlatch'soutputwhen
Clktransitionsfrom0to1(risingedge).
•Synchronization:Theslavelatchchanges
stateonlyattherisingedgeofClk,
ensuringsynchronizationtotheclock
signal.
109

110. CharacteristicsApplicationsFlip-Flop Type
Data input (D),
Output changes
on clock edge
Data storage,
Synchronization,
Shift registers
D Flip-Flop
Set, reset, or
toggle based on
J and K inputs
Counters, Sequence
generation, Control
logic
JK Flip-Flop
Toggles on clock
pulse when T = 1
Frequency division,
Binary counters,
State machines
T Flip-Flop
Changes on
clock edge
(rising/falling)
Synchronous
circuits, Timing
circuits
Edge-
Triggered
Flip-Flop
110