computer architecture_new_jjsdjsnjcj.pptx

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1. Course Objectives This course aims to learn the basic structure and operations of a computer. The course is intended to learn ALU, pipelined execution, parallelism and multi-core processors. The course will enable the students to understand memory hierarchies, cache memories and virtual memories.

2. Course Outcomes CO 1 Discuss the basics structure of computers, operations and instructions. CO 2 Design arithmetic and logic unit. CO 3 Analyze pipelined execution and design control unit. CO 4 Analyze parallel processing architectures. CO 5 Examine the performance of various memory systems CO 6 Organize the various I/O communications.

3. Syllabus Unit Titles: Unit I Basic Structure of a Computer System Unit II Arithmetic for Computers Unit III Processor and Control Unit Unit IV Parallelism Unit V Memory & I/O Systems

4. Syllabus – Unit I UNIT-I BASIC STRUCTURE OF A COMPUTER SYSTEM   Functional Units – Basic operational concepts –– Instructions: Operations, Operands – Instruction representation – Instruction Types – MIPS addressing, Performance

5. Syllabus – Unit II UNIT-II ARITHMETIC FOR COMPUTERS Addition and Subtraction – Multiplication – Division – Floating Point Representation – Floating Point Addition and Subtraction.

6. Syllabus – Unit III UNIT-III PROCESSOR AND CONTROL UNIT A Basic MIPS implementation – Building a Datapath – Control Implementation Scheme – Pipelining – Pipelined datapath and control – Handling Data Hazards & Control Hazards.

7. Syllabus – Unit IV UNIT-IV PARALLELISM Introduction to Multicore processors and other shared memory multiprocessors – Flynn’s classification: SISD, MIMD, SIMD, SPMD and Vector – Hardware multithreading – GPU architecture.

8. Syllabus – Unit V UNIT-V MEMORY & I/O SYSTEMS Memory Hierarchy – memory technologies – Cache Memory – Performance Considerations , Virtual Memory,TLB’s – Accessing I/O devices – Interrupts – Direct Memory Access – Bus Structure – Bus operation.

9. Text Books Book 1: Name: Computer Organization and Design: The Hardware/Software Interface Authors: David A. Patterson and John L. Hennessy Publisher: Morgan Kaufmann / Elsevier Edition: Fifth Edition, 2014 Book 2: Name: Computer Organization and Embedded Systems Interface Authors: Carl Hamacher , Zvonko Vranesic , Safwat Zaky and Naraig Manjikian Publisher: Tata McGraw Hill Edition: Sixth Edition, 2012

10. Introduction What is mean by Computer Architecture? Hardware parts Instruction set Interface between hardware & software

11. Introduction What is meant by Computer Architecture? Computer architecture encompasses the specification of an instruction set and the functional behavior of the hardware units that implement the instructions.

12. Introduction

13. Technology Evolution

14. UNIT-I BASIC STRUCTURE OF A COMPUTER SYSTEM Topics: Functional Units Basic operational concepts Instructions: Operations, Operands Instruction representation Instruction Types MIPS addressing mode Performance

15. Functional Units Also called as Datapath

16. Functional Units

17. Functional Units Input unit Output unit Memory unit Arithmetic Logic unit Control unit

18. Functional Units Input unit

19. Functional Units Output unit

20. Functional Units Memory unit

21. Functional Units

22. Functional Units Arithmetic & Logic unit and Control unit

23. Basic Operational Concepts Unit I

24. Connection between the processor and the main memory Code Snippet: Load R2, LOC Add R4, R3, R2 Store LOC, R4

25. IR & PC Instruction Register: The instruction register (IR) holds the instruction that is currently being executed. Program Counter: The program counter (PC) contains the memory address of the next instruction to be fetched and executed.

26. Instructions

27. Steps in program translation ISA

28. Translations

29. Machine vs Assembly Language Machine Language Assembly Language A particular set of instructions that the CPU can directly execute – but these are ones and zeros Ex: 0100001010101 Assembly language is a symbolic version of the equivalent machine language Ex: add a,b

30. Mnemonics

31. Instructions Instruction Set: The vocabulary of commands understand by a given architecture. Some ISA: ARM Intel x86 IBM Power MIPS SPARC Different CPUs implement different set of instructions.

32. MIPS MIPS - M icroprocessor with I nterlocked P ipeline S tages Features: five-stage execution pipeline: fetch, decode, execute, memory-access, write-result regular instruction set, all instructions are 32-bit three-operand arithmetical and logical instructions 32 general-purpose registers of 32-bits each only the load and store instruction access memory flat address space of 4  GBytes of main memory (2^32 bytes)

33. MIPS Assembly Language Categories: Arithmetic – Only processor and registers involved (sum of two registers) Data transfer – Interacts with memory (load and store) Logical - Only processor and registers involved (and, sll ) Conditional branch – Change flow of execution (branch instructions) Unconditional Jump – Change flow of execution (jump to a subroutine)

34. Arithmetic