ERTS UNIT2.pptx 2.2.5.industry internship/summer training a)IV report for Academic year 21-22 b)Internship with feedback Academic year 2019-2010 Academic year 2020-2021 Academic year 2021-2022 Marks 15

Sub Criteria Description Documents for this criteria As per NBA ECE SAR To be common with
2.2.5.industry internship/summer training a)IV report for Academic year 21-22
b)Internship with feedback Academic year 2019-2010
Academic year 2020-2021
Academic year 2021-2022
Marks 15

2.1.1 Program Curriculum a)University curriculum for attaining the Program Outcomes(POs) & Program Specific Outcomes(PSOs
b) identified curricular gaps a)Reg2013
Reg2017
b)Reg2013
Reg2017
Marks 10
2.1.2 content beyond the syllabus for the attainment of POs & PSOs a)identified gaps included in the curriculum.(e.g. letter to university/BOS)
b) Delivery details of content beyond syllabus c)content beyond syllabus with the POs & PSOs Academic year 2019-2010
Academic year 2020-2021
Academic year 2021-2022
Marks 10
2.2.1. improve quality of Teaching Learning a) Institution Department academic calendar and adherence with university schedule
b) various instructional methods and pedagogical proof c)Methodologies to support weak students and encourage bright students
d)Quality of classroom teaching (Observation in a Class) Conduct of experiments (Observation in Lab)
e) Continuous Assessment in the laboratory
f)Student feedback of teaching learning process and actions taken Academic year 2019-2010
Academic year 2020-2021
Academic year 2021-2022
Mark 25
2.2.2. internal semester Question papers, Assignments and Evaluation a) internal semester question paper setting and evaluation
b) Assignment and its relevance to COs Academic year 2019-2010
Academic year 2020-2021
Academic year 2021-2022
Marks 20
2.2.3. Quality of student projects a)Project report with POs and PSOs
b)Best project and prototype
c)Paper published/Awards by projects Academic year 2019-2010
Academic year 2020-2021
Academic year 2021-2022
Marks 25
2.2.4. Initiatives related to industry interaction a)TESOLVE Lab
b)CISCO Lab
with impact analysis Mark 15

1. UNIT II ARM PROCESSOR AND PERIPHERALS P.JEYALAKSHMI HoD /ECE IV-ECE

2. ARM Stacks Stacks are highly flexible in the ARM architecture, since the implementation is completely left to the software. Stack Instructions.  The ARM instruction set does not contain any stack specific instructions like push and pop. The instruction set also does not enforce in anyway the use of a stack. Push and pop operations are performed by memory access instructions, with auto-increment addressing modes. Stack Pointer.  The stack pointer is a register that points to the top of the stack. In the ARM processor, there are no dedicated stack pointer registers, and any one of the general purpose registers can be used as the stack pointer. Stack Types.  Since it is left to the software to implement a stack, different implemenation choices result different types of stacks. There are two types of stack depending on how the stack grows. Ascending stack In a push the stack pointer is incremented, i.e the stack grows towards higher address. Descending stack In a push the stack pointer is decremented, i.e the stack grows towards lower address.

3. Cont…. There are two types of stack depending on what the stack pointer points to. Empty stack Stack pointer points to the location in which the next item will be stored. A push will store the value, and increment the stack pointer. Full stack Stack pointer points to the location in which the last item was stored. A push will increment the stack pointer and store the value. Four different stacks are possible - full-ascending, full-descending, empty-ascending, empty-descending. All 4 can be implemented using the register load store instructions.

4. LDM/STM for Stack Operations Traditionally, a stack grows down in memory, with the last “pushed” value at the lowest address. The ARM also supports ascending stacks, where the stack structure grows up through memory. The value of the stack pointer can either: Point to the last occupied address (Full stack) and so needs pre-decrementing/incrementing ( ie before the push) Point to an unoccupied address (Empty stack) and so needs post-decrementing/incrementing ( ie after the push) The stack type to be used is given by the postfix to the instruction: STMFD / LDMFD : Full Descending stack STMFA / LDMFA : Full Ascending stack. STMED / LDMED : Empty Descending stack STMEA / LDMEA : Empty Ascending stack Note: ARM Compilers will always use a Full descending stack.

5. Stack Examples STMFD sp!, {r0,r1,r3-r5} r5 r4 r3 r1 r0 SP Old SP STMED sp!, {r0,r1,r3-r5} r5 r4 r3 r1 r0 SP Old SP r5 r4 r3 r1 r0 STMFA sp!, {r0,r1,r3-r5} SP Old SP 0x400 0x418 0x3e8 STMEA sp!, {r0,r1,r3-r5} r5 r4 r3 r1 r0 SP Old SP

6. LDM/STM Alias Names STMIA, STMIB, STMDA, STMDB are the same instructions as STMEA, STMFA, STMED, STMFD , respectively LDMIA, LDMIB, LDMDA, LDMDB are also the same instructions as LDMFD, LDMED, LDMFA, LDMEA , respectively The later names are useful when working with stacks

7. LDM/STM: ^ modifier The ^ modifier changes the behavior of LDM and STM. There are 2 cases: If the PC is not included in the register list: A ‘^’ specifies a transfer to/from the user register bank Used in exception handlers to inspect/modify the user mode registers Example: stmia r0,{ sp,lr }^ @ Transfer SP_user and LR_user to memory ldr r1,[r0] @ R1= SP_user ldr r2,[r0,#4] @ R2= LR_user If the PC is included in the register list (LDM only): The SPSR is copied to CPSR Appropriate for exception return Example: ldmfd sp !, {r4-r7,pc}^ @ return from SWI

8. UNIT II ARM PROCESSOR AND PERIPHERALS G.JEYALAKSHMI HoD /ECE

9. TIMER The LPC2148 has two functionally identical general purpose timers: Timer0 and Timer1 . These both timers are 32-bit along with 32-bit prescaler . Timer allows us to generate precise time delay. For Example: In our blink LED example project, we’ve generated random delay of approximate 1 Sec. but using Timers we can generate accurate time delay. Apart from this we can use timers as pulse width modulator and also as free running timer.

10. How Timers in LPC2148 ARM7 Microcontroller Works? The heart of timers of the LPC2148 Microcontroller is a 32-bit free running counter, which is designed to count cycles of the Peripheral Clock (PCLK) or an external clock, this counter is programmable with 32-bit prescaler The tick rate of the Timer Counter (TC) is controlled by the 32-bit number written in the Prescaler Register (PR) in the following way. There is a Prescale Counter (PC) which increments on each tick of the PCLK. When it reaches the value in the prescaler register, the timer count is incremented and the Prescaler Counter (PC) is reset, on the next PCLK. This cause the timer counters to increment on every PCLK when PR=0, every 2 PCLKs when PR=1, etc.

11. TIMER REGISTERS in LPC2147 ARM7

12. PWM in LPC2148 ARM7 Microcontrolle R Pulse Width Modulation (PWM) is very useful technique for controlling analog circuits with processors digital outputs. PWM used in a wide variety of applications ranging from measurement and communications to power control. As PWM is famous technique to generate a signal of varying duty cycle. Here we will use it to control brightness of LED using LPC2148. Why we need PWM? As we all know that microcontrollers do everything with ones and zeros. That means microcontroller works with 3.3V and 0V as digital 1 & 0. It can’t produce for example 1V or 2.5V or any other value different than 0V and 3.3V. Here PWM feature allows us to generate any voltage level between 0V and 3.3V. Now we will see how it’s been done using PWM so that we will control brightness of LED. This is probably the best way to see effect of PWM. Before we proceed any further let’s discuss little bit about duty cycle

13. Duty Cycle When signal is HIGH, we call this “ON time”. To describe amount of “on time”(TON), we use the concept of duty cycle. Duty cycle is measured in percentage. The percentage duty cycle describe the performance of a digital signal ON over an interval or period of time.  This period is the inverse of the frequency of the waveform. If digital signal spends half of time ON and remaining OFF, we would say this digital signal has duty cycle of 50%. If percentage is higher than 50% that means digital signal spends more time in HIGH state than LOW state then we would say duty cycle is higher than 50%.

14. PWM Duty Cycle Pulse PWM Duty Cycle Pulse Above graph represents waveform of 50%, 75% & 25% duty cycle. 100% duty cycle would be the same as setting the voltage to 3.3V (HIGH). 0% duty cycle would be same as 0V or grounding the signal. The relation and calculation has been evaluated by following equations: Equation for Calculation Duty Cycle

15. PWM in LPC2148 ARM7 PWM in LPC2148 ARM7 looks complicated than the general purpose timers. However it is really an extra general purpose timer with some additional hardware. The PWM in LPC2148 is capable of producing six channels of single edge controlled PWM or three channel of dual edge controlled PWM. The Phillips LPC2148 has 6 channels of pulse width modulation. There are 7 registers to accommodate the PWM with register 0 being used to set base frequency (f =1/T). Thus since there is only one base frequency register all 6 channels must have base frequency.

16. PWM in LPC2148 can be single edge or double edge. In double edge PWM ending point of pulse and starting point of the pulse is a variable and can be set each cycle. In single edge PWM only the ending edge of the PWM is a variable and the starting edge is always set at the base frequency. Single edge requires one register (plus the base register) so that you can have 6-single edge channels of PWM on the LPC2148. For double edge PWM. You need a base register plus a starting edge register plus and ending edge register so that only 3-channels of double edge PWM is available on the LPC2148. You can mix single and double edge channels as long as you don’t run out of 6 available registers.

17. Registers: PWM in LPC2148 ARM7 

18. UNIT II ARM PROCESSOR AND PERIPHERALS P .JEYALAKSHMI HoD /ECE VCE

19. ARM9(TDMI) ARM9TDMI

20. ARM9(TDMI) ARM7 microarchitecture is getting old and will be replaced with ARM9 ARM9 realizes the same (v4T) instruction set as ARM7 and is thus binary compatible Pipeline length is 5 stages instead of ARM7 3 stages. This allows for faster clocking. Available with TDMI extensions • ARM92x: ARM9TDMI and caches as a macrocell •Caches are separate for instructions and data (Harvard Architecture) The ARM9TDMI family are used for high performance applications that previously could not be implemented at the same cost. This family of cores was developed with twice the performance of the ARM7TDMI and without changes to the architecture. It is ideally suited for the next generation of cell phones, personal digital assistants, multi-function peripherals and fast printers, and set-top box applications

21. ARM9E Core Architecture

22. features 32-bit load/store RISC architecture Efficient 5-stage pipeline ARM and Thumb instruction sets 37 x 32-bit registers 32-bit ALU and barrel shifter Enhanced 32-bit MAC block ETM9 interface AMBA AHB interface Coprocessor interface Synthesizable or soft IP

23. FEATURES As mentioned hard macrocells always have been the ultimate answer for optimized performance and die size in any given processor design. But newer synthesized design flows are pushing the envelope for SoC applications. The ARM9E family was built upon the standard set by the ARM9TDMI family, but it also provides freedom for defining the cache and tightly coupled SRAM configurations used by the core. It was also the first family of CPUs designed to the AHB bus of the AMBA 2.0 specification.

24. FEATURE Another key technological enhancement to this family of CPUs includes DSP extensions for true realtime systems. This improvement to the architecture introduces additional multiply and saturated math instructions for use by complex DSP algorithms. This family is also fully code compatible with ARMv4T architecture cores. Lastly, to enhance the debug capabilities already common in ARM CPUs, the Embedded Trace Macrocell interface was added. This interface enables real-time debugging of complex real-time systems.