Peak Power Reduction By Controlling Clock Using Path...
Peak Power Reduction by controlling clock using path clustering
Sindhu V1 and Mr.P.Nagarajan2
1PG Scholar, Dept of ECE, Vivekanandha College of Engineering for Women,
[email protected]
2Assistant professor,Dept of ECE, Vivekanandha college of engineering for Women
,
[email protected]
Abstract Power reduction is an major challenge in the integrated circuit design since it degrades
the chip performance the reliability. Frequent transistor switching caused due to large IR voltage
drops gives raise to timing violations and logic failures. A new clock control strategy is been
introduced in this paper such that the simultaneous switching of the combinational paths is
minimized. This is achieved by clustering the delay slacks having similar slack values. Once the
paths are identified based on the path delays and their slack values the clustering algorithm
determines the path to clusters in a load balanced manner based on the slack values and each
cluster will have a phase shift possible on its clock depending on the slack.
INTRODUCTION
Low power has emerged as a major goal in today s electronics industry. The motivations for
reducing power consumption differ from application to application. For high performance, portable
computers, such as laptop and notebook computers, the goal is to reduce the power dissipation of
the electronics portion of the system to a point that is about half of the total power dissipation
(including that of display and hard disk).
Peak
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