IEM 27th June 24F_by Jadavpur Professor.pptx

Lecture on Microstrip Antenna

1. Know Y our Today’s Speaker Prof. Subir Kumar Sarkar has completed his B. Tech, M. Tech and PhD (Tech) from Institute of Radiophysics and Electronics, University of Calcutta and Post Doctoral from Virginia Commonwealth University (VCU), USA . He worked around 10 years in industry like Oil and Natural Gas Corporation (ONGC) as an Executive Engineer &30 years in Universities (8 Years IIEST (formerly BESU) and 22 years in Jadavpur University) in different capacities. After retirement from Jadavpur University I joined IIEST a few months back as a visiting Professor.   He was the Head of the Dept of Electronics and Telecommunication Engg , Jadavpur University during 2011-2013.   He was the coordinator of the Evening course , M. Tech in “VLSI Design and Microelectronics Technology” for ten years and the Co-ordinator of IC Design & Fabrication Centre , Jadavpur University more than six years. He has authored 6 Engineering text books published by CRC Press USA, Artech House USA , PAN STANFOPRD USA, S.Chand & Company Pvt. Ltd.,  Inda He has already guided 60 PhD scholars ( 5 more registered and currently working) 21 R&D projects( with Total funding of more than two crores rupees) sponsored by different Govt. of India funding agencies have been completed. Published more than 735 technical research papers in archived International/ National journals(281) and peer reviewed conferences(454) . Research Area(s): Nanodevices and low power VLSI circuits, Computer networks , Digital Watermarking, RFID and Sensors & their applications.   Foreign Visit: He has visited several countries like Australia, USA, France, the United Kingdom, Switzerland, Japan , Thailand and Bangladesh as Keynote speaker, Special Guest of Honour , Invited speaker, for training, presenting papers and visiting sophisticated laboratories as a part of his collaborative research activities.   He has delivered around 133 Plenary/ Keynote/ Invited talks, 20 IEEE DL talks, four tutorial talks and chaired around 50 technical sessions in various academic programs. Prof. Sarkar has acted as a member of NBA team for evaluating more than 30 Engineering & Technology Institutes all over India. Honored with the prestigious IETE – Brig M L Anand Award-2019 for notable expertise in Network domain as is evident from his 183 research papers , 20PG and 18 PhD thesis guidance in Network Area and publication of two books ( CRC press & Artech House) whose review came in IEEE communication Magazine and has stupendous citation record of 710 and Prof. S K Mitra Memorial Award-2019 from IETE 2019 for one of his research work as the best research oriented paper among all the papers published in IETE Technical Review Journal in the year 2018-2019. Professional Membership: Senior Member of IEEE, IEEE Distinguished Lecturer of Electron Device Society, Life fellow of IE(India) and IETE, Life member of ISTE and Life member of Indian Association for the Cultivation of Science (IACS).   He has successfully organized four IEEE sponsored International Conferences as Convener in 2004 & 2022 and as General Chair in 2012 & 2019 . 26-06-2024 Prof. Subir Kumr Sarkar, Jadavpur University

2. Serial no. Event name Numbers of Event Serial No. Event name No. of Event 1. Research Publications Total: 735 Nos , Journal: 281 Nos Conference: 454 Nos 9. Institutes accredited as a member of NBA Team 50 Nos 2. PhD guidance: Total: 60 Nos , Device Area: 36 Nos Other Areas : 24 Nos 10. Session Chair 50 Nos 3. P.G. thesis guidance Total : 105 Nos , Device: 71 Nos , Others: 34 Nos 11. Foreign Trips 13 Nos 4. Invited Talk Total: 134 Nos , Tutorial talk: 4 Nos Keynote speech: 11 Nos , Plenary speech: 5 Nos , Guest lecture: 4 Nos , Invited speech: 114 Nos 12. Awards Award: 5 Nos Best Paper Award: 6 Nos 5. IEEE Distinguished Lecture talk 21 Nos 13. Faculty Training Program organized as Coordinator 13 Nos 6. R&D Funded Projects Total: 21 Nos [Total funding more than 2Crores ] As Principal Investigator (PI) : 18 Nos As co-Investigator: 3 Nos 14. MOU made with other Institutes as Coordinator of IC Design & Fabrication Centre 3 Nos 7. Book Published 6 Nos 15. Collaborative Research work with others: 10 Nos 8. Book Chapter Published 24 Nos Performance Table of Prof. Subir Kumar Sarkar Current Position: Visiting Professor at IIEST, Shibpur . Former Professor & Coordinator of ( i ) IC Design and Fabrication Centre &(ii) Evening M Tech Course in VLSI Design& Microelectronics Technology, Dept. of Electronics and Telecommunication Engg , Jadavpur University, India

3. Performance Table of Prof. Subir Kumar Sarkar Past Position: Professor, Coordinator of ( i ) IC Design and Fabrication Centre & ( ii) Evening M Tech Course in VLSI Design& Microelectronics Technology, Dept . of Electronics &Telecommunication Engg , Jadavpur University, India Sl no. Event name Numbers of Event Sl No. Event name No. of Event 1. Research Publications Total: 735, Journal: 281 Conference: 454 9. Institutes accredited as a member of NBA Evaluation Team 50 2. PhD guidance: Total: 60 , Device Area: 38 Other Areas : 22 10. Session Chair 50 3. P.G. thesis guidance Total : 85, Device:52 , Others:33 11. Foreign Trips 13 4. Invited Talk Total: 134Nos , Tutorial talk: 4 , Keynote speech: 12, Plenary speech : 5, Guest lecture : 4 , Invited speech :113 12. Awards Award: 5 , Best Paper Award: 6 5. IEEE Distinguished Lecture talk 21 Numbers 13. Faculty Training Program organized 13 6. R&D Funded Projects Total: 21 Nos As Principal Investigator ( PI) : 18 As co-Investigator: 3 14. MOU made with other Institutes as Coordinator of IC Design & Fabrication Centre 3 7. Book Published 6[CRC Press, Artech House etc ] 15. Collaborative Research work with others: 10 8. Book Chapter Published 24

4. Dr. Anupam Karmakar Dr. C. Puttamadappa Dr. Jitendra Bera Dr. P.K. Sahu Dr. T.G.Basavaraju Dr. P. C. Pradhan Dr. B. Maji Dr. Satya Sopan Mahato Dr. T. S. Das Dr. Tapas Kumar Maiti Dr. Vijay H. Mankar Dr. Tirthankar Datta Dr. Ankush Ghosh Dr.S . R. Biradar Dr. Gowrishankar S Dr. S. Dogra Dr.Sanjoy Deb Dr. K . Majumder Dr. G.P.S Mishra Dr. N Basanta Singh Dr.C. J . Clement Singh Dr. K. Senthil Kumar Dr. Rajanna K M Dr. D. Samanta Dr. Jayanta Gope Dr. Abhishek Basu Dr. Suman Basu Dr.S.Majumder Dr. Anindya Jana Sri. Bijoy Kantha Dr. Asish Kumar De 6/26/2024 Prof. Subir Kumar Sarkar, Jadavpur University 5 Research Group of Prof. Subir Kumar Sarkar Guided 60 PhD scholars from all over India( Kashmir to Kanyakumari)

5. Research Group of Prof. Subir Kumar Sarkar Some moments of MSSND-2019 organized by Prof. Subir Kumar Sarkar (as General Chair) Inaugural ceremony Group Photo Session Award Speech 26-06-2024 Prof. Subir Kumr Sarkar , Jadavpur University 7

6. “ If you want to walk fast, walk alone. But if you want to walk far, walk together ” --------- Ratan Tata "Aspire to inspire before we expire." ----- Subir Kumar Sarkar

7. 26-06-2024 Prof. Subir Kumr Sarkar, Jadavpur University 9 Issues and Challenges in VLSI Design Currently a Visiting Professor in the Dept. of Electronics and Telecommunication Engineering Indian Institute of Engineering Science and Technology(IIEST) , Shibpur , West Bengal ======================================================================================================= Prof( Dr. ) Subir Kumar Sarkar Senior Member IEEE, IEEE Electron Device Society Distinguished Lecturer Life Fellow of IETE and IE, LM ISTE, Life Member of Indian Association for the Cultivation of Science Former Member of The Executive Council and The COURT of Jadavpur University. Former Professor and Head Former Coordinator of IC Design and Fabrication Centre & Evening PG Course of VLSI Design. Dept. of Electronics and Telecommunication Engineering , Jadavpur University, India Occasion: FDP at IEM, Salt Lake. Date: 27 th June 2024 Venue: Institute of Engineering and Management, Salt Lake , Kolkata, India

8. Outline VLSI Design VLSI Design Flow VLSI Applications One Real life system Design VLSI Design issues Noise Margin Questionnaire Session Conclusion

9. What is VLSI Design ? 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Tuning the Power Performance in Low Power VLSI Design

10. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Tuning the Power Performance in Low Power VLSI Design

11. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

12. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

13. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

14. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

15. What is the limitation of contemporary CAD tools? In RTL coding there is no provision to use Multi-Vt , Multi-Vdd, Body biasing and power gating in RTL synthesis. So, the static power reduction techniques cannot be used. As supply voltage and the operating frequency are also not handled at the RTL level, the dynamic power can be reduced primarily by reducing the switching activity . Commonly used techniques in RTL synthesis to reduce are: Bus encoding Clock gating FSM state assignment 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

16. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Searching Befitting Devices for Modern VLSI Circuits

17. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Tuning the Power Performance in Low Power VLSI Design

18. 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University Tuning the Power Performance in Low Power VLSI Design

19. Pad Metal1 Via Metal2 I/O Data Path ROM/ RAM PLA A/D Converter Random logic Basic Components in VLSI Circuits Devices Transistors Logic gates and cells Functional blocks Interconnects Local signals Global signals Clock signals Power/ground nets

20. VLSI Design Flow behavioral representation Logic Synthesis logic simulation structural representation Circuit Design circuit analysis Physical Synthesis structural representation extraction & verification Fabrication physical representation specification Function/architecture Design System Specification functional simulation Packaging

21. VLSI Design Flow (Contd.)

22. A Real-life System Design. "Do not go where the path may lead, go instead where there is no path and leave a trail." – Ralph Waldo Emerson

23. Problem Definition : This problem deals with the design of a control unit for a simple coin operated Tea vending machine. The Tea costs Rs . 3 and the machine accepts Rs . 2 and Re. 1 coins. Change should be returned if more than Rs . 3 is deposited. No more than Rs . 4 can be deposited on a single purchase. Therefore, the maximum change is Re. 1. A block diagram of the Tea vending machine is given in the following figure. The control unit has two inputs N and D which are the outputs of the coin detector. The coin detector generates a 1 on signal N if a Re. 1 coin is deposited and a on signal D if a Rs . 2 coin is deposited. The N and D lines automatically reset to 0 on the next clock pulse. We shall assume that it is physically impossible to insert 2 coins at the same time and therefore, we cannot have N=D=1 in the same clock period. The control unit has 2 outputs R and C. The Tea is released by a 1 appearing on signal R. The state of the control unit represents the total amount of money deposited for the current purchase. Design the Tea Vendig machine control unit.

24. Steps for Design : Step 1: Drawing the state diagram Step2: Drawing the state table Step3: Encoding or assigning various states with binary codes and drawing the state Transition table. [ No of bits for encoding N independent states is Log 2 N ] If N=8 then No of bits for encoding 8 independent states is Log 2 8 = Log 2 2 3 = 3Log 2 2 = 3x1=3bits Step4 : Using logic reduction techniques, reduce the number of logic variables required Step5: Drawing the Logic diagram based on the equations developed in the step4.

25. Solution: State Diagram Drawing PS NS/RC State D=0 D=1 S S 1 /00 S 2 /00 S 1 S 2 /00 S 3 /10 S 2 S 3 /10 S 4 /11 S 3 S /00 S /00 S 4 S /00 S /00 Since here, only N(1Re) and D(2 Rs ) can be ‘1’ at a given time, we take only D=0[ means N=1] and D=1 in our state table . State Table: [ N or D/RC ] If N=8 then No of bits for encoding 8 independent states is Log 2 8 = Log 2 2 3 = 3Log 2 2 = 3x1=3bits State Code for the state   y 2 Y 1 Y S S 1 1 S 2 1 S 3 1 1 S 4 1

26.   PS NS D=0 D=1 State y 2 y 1 y Y 2 Y 1 Y /RC Y 2 Y 1 Y 02 /RC S 001/00 010/00 S 1 1 010/00 011/10 S 2 1 011/10 100/11 S 3 1 1 000/00 000/00 S 4 1 000/00 000/00 Dy 2 \y 1 y 00 01 11 10 00 1 1 01 x x x 11 x x x 10 1 K-MAP for Y0 Y = y 2 / y / D / + y 2 / y 1 / y D

27. Dy 2 \y 1 y 00 01 11 10 00 1 1 01 x x x 11 x x x 10 1 1 K-Map for Y1: K-Map for Y2: Dy 2 \y 1 y 00 01 11 10 00 01 x x x 11 x x x 10 1 Y 1 = y 2 / y 1 / y + y 2 / y 1 / D + y 2 / y 1 y / D / ஃ Y 2 = y 2 / y 1 y / D   PS NS D=0 D=1 State y 2 y 1 y Y 2 Y 1 Y /RC Y 2 Y 1 Y 02 /RC S 001/00 010/00 S 1 1 010/00 011/10 S 2 1 011/10 100/11 S 3 1 1 000/00 000/00 S 4 1 000/00 000/00

28. Dy 2 \y 1 y 00 01 11 10 00 1 01 x x x 11 x x x 10 1 1 Dy 2 \y 1 y 00 01 11 10 00 01 x x x 11 x x x 10 1 K-Map for R K-Map for C Hence: ஃ Y = y 2 / y / D / + y 2 / y 1 / y D ஃ Y 1 = y 2 / y 1 / y + y 2 / y 1 / D + y 2 / y 1 y / D / ஃ Y 2 = y 2 / y 1 y / D ஃ R = y 2 / y 1 y / + y 2 / y 1 / y D ஃ C = y 2 / y 1 y / D ஃ C = y 2 / y 1 y / D R = y 2 / y 1 y / + y 2 / y 1 / y D

29. The circuit Diagram for Tea Vending Machine :  

30. Back to talk again

31. What is the average power dissipation of a MOS Transistor? What will happen if we ignore ? 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University MOSFET Scaling

32. 38 Can Moore’s law keep going? Power dissipation=greatest obstacle for Moore’s law! Modern processor chips consume ~100W of power of which about 20% is wasted in leakage through the transistor gates. The traditional means of coping with increased power per generation has been to scale down the operating voltage of the chip but voltages are reaching limits due to thermal fluctuation effects . 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University MOSFET Scaling

33. Present day transistors dissipate 0.1- 1 m W of power per bit flip Assume a transistor density of about 10 8 /cm 2 (Pentium IV) Chip is dissipating about 10-100 W/cm 2 (if all transistors switch simultaneously) Power dissipated in a 10 cm 2 chip is 100 W - 1 kW The end of the roadmap? Approximately 1 kW/cm 2 power removed from a silicon chip using traditional heat sinking techniques (Tuckerman and Pease) 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University MOSFET Scaling

34. Assume that transistors still dissipate 0.1 m W of power per bit flip: Because energy dissipation decreases with improved materials and devices, but clock speed will also go up so that power dissipation will remain approximately constant in the near future. Assume 10-nm gate length devices (7nm in production by Intel, 6 nm demonstrated at IBM) and a transistor density of 10 11 /cm 2. Power dissipation is now 10 kW/cm 2 [ i.e. 0.1 m W x 10 11 /cm 2 = 10 kW/cm 2 ] Chip size may be 100 cm 2. Power dissipated in the chip is 0.1 MW [10 kW/cm 2 x 100 cm 2 = 0.1 MW ] more power dissipation than in a rocket nozzle !! The chief problem facing designers comes down to size. Moore's Law works largely through shrinking transistors, the circuits that carry electrical signals. By shrinking transistors, designers can squeeze more transistors into a chip. However, more transistors means more electricity and heat compressed into an even smaller space. Furthermore, smaller chips increase performance but also compound the problem of circuitry. Could be unmanageable thereby Threatens Moore’s law Near Future 6/26/2024 Prof. Subir Kumar Sarkar, Dept. of ETCE, Jadavpur University

35. In his Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP. 26-06-2024 Prof. Subir Kumar Sarkar , Jadavpur University MOSFET Scaling

36. Questionnaires Session-I "Logic will get you from A to B. Imagination will take you everywhere." – Albert Einstein

37. Q1. Which gate is known as coincidence detector? Answer :   XNOR gate is known as coincidence detector . Q2: Under what condition t here is no short circuit power dissipation in a static CMOS circuit ? ANS: When Vdd < ( Vtn + ! Vtp !), t here is no short circuit power dissipation in a static CMOS circuit. Q3: When Vdd < ( Vtn + ! Vtp !), why t here is no short circuit power dissipation in a static CMOS circuit ? ANS: only one tansistor can turn on at a time when Vdd < ( Vtn + ! Vtp !). Since both the transistors cannot be turned on simultaneously,there is no short circuit power dissipation. Q4: What is the noise related limitation of CMOS inverter ? Ans : As the output voltage of the of the nMOS network is deteriorated by a threshold voltage V Tn , the output can only be pulled upto V DD - V Tn .

38. Q5. As source drain voltage increases, channel depth a) increases at the drain and source ends, b) decreases at the drain end c) logarithmically increases at the drain end , d) exponentially increases at the drain and source ends AnswerQ5: b Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases Q6. While designing a digital system, the main objectives are ANS: (A) Low cost , (B) Less number of gates , (C) Increased Speed , (D)Low power dissipation Q7. Which gate is known as coincidence detector? Answer:  XNOR gate is known as coincidence detector . Q8. What tools Do We Need To Generate Hardware From VHDL Model? ANS: We need following tools Simulation tool. Synthesis tool. Implementation tool.

39. SOME METHODS TO INTERFACE CMOS ICs WITH TTL ICs Q: Can CMOS ICs be connected as a load of TTL ICs and Vice – versa? ANS: CMOS gate can be directly connected to TTL gates. Usually, CMOS gates require supply voltages of +5V to +15V. However, TTL gates require only +5-volt supply. Hence, CMOS gates can drive TTL directly. But, TTL does not have enough power to drive the CMOS directly. Hence, a pull-up resistor R pull -up can be used , which will deliver the current required to drive the CMOS.

40. contd … In the previous case, we assume both the TTL and CMOS gates to be driven from the same supply of 5V. Considering CMOS supply to be different from that of the TTL. Now, we consider CMOS is driven by 10V and TTL by 5V. Then, a CMOS buffer may be introduced in between the first CMOS and the TTL. The first CMOS will drive the second CMOS buffer, which will in turn drive the TTL directly .

41. issue with CMOS : Issue: The nMOS can pass ‘0’ perfectly but cannot pass ‘1’ without degradation! Whereas the pMOS can pass ‘1’ perfectly but cannot pass ‘0’ without degradation! In order to get strong output level PMOS and NMOS are connected together[ in parallel] so that the imperfect feature of one transistor will be made up by the other . The gate consists of one NMOS and one PMOS transistor, connected in parallel is called transmission gate(TG). The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C .

42. Questionnaires Session-II Interactive session to focus on the Impact of AI & ML in VLSI Design

43. What is the future of VLSI?                               The future of VLSI technology looks promising, with  new innovations such as artificial intelligence (AI) and the Internet of Things ( IoT ) driving the demand for more powerful and energy-efficient chips . With technological upgradation, AI and Machine Learning are transforming every industry with exceptionally great inputs. Referring to the VLSI industry, there has been a considerable amount of required changes done by machine learning.  Machine Learning (ML) has benefited the VLSI industry so far by using  EDA tools  to their maximum usage which helps in reducing design time and cost to production.  Machine learning in VLSI design helps EDA tools find the better solution for use case scenarios by predicting the defects on the chip which in turn saves loss during production. Machine learning in VLSI: Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels. It , in turn, improves the IC yield and reduces the manufacturing turnaround time.

44. What can machine learning do for design? The three ways a designer can intersect with machine learning:  Using ML as a design tool ( AI and design collaboration for interface design)  Designing for AI (building AI system with ML engineers)  Design AI interfaces ( Interaction design of AI systems) Which algorithm to use in machine learning? Linear regression is one of the most popular and simple machine learning algorithms that is used for predictive analysis. Is AI related to VLSI? #AI (Artificial Intelligence) and #VLSI (Very Large Scale Integration) are closely related, as VLSI plays a critical role in developing specialized hardware for AI algorithms. VLSI is used to design and manufacture hardware that can accelerate AI algorithms, which are typically computationally intensive.

45. Benefits of machine learning in VLSI design: 1) Ease in the verification process: As the data generated from complex chips keep exploding, machine learning in VLSI design and verification are much needed to ensure smooth functioning without compromising on its performance and cost.  Consider  RTL design course  (a VLSI course) for a better understanding ML helps to formulate test cases and suggest better design flows for RTL implementation.  From RTL design and its verification till synthesis, it helps to focus on improving the current ongoing strategies . 2) Time-saving:  A technique like  linear regression  associated with ML helps to break down the complexity and resulting in faster verification. 3 ) 3 P’s ( Power, Performance, Price) : Synopsys and Cadence are some of the EDA tools which are constantly utilizing machine learning techniques for more efficient design stimulation and revamp the 3 P’s. Conclusion: The high-end solutions driven by machine learning techniques in chip designs and ease in the verification process are commendable. They have been bringing innovations in the VLSI fields and helping to save the most essential asset- time! 

46. CONCLUSION

47. Finally My Desire If I had my life to live again, I would still pursue an academic career -- there is no better choice. My Declaration I have worked: around 10 years in industry like Oil and Natural Gas Corporation a Govt. of India Undertaking Navaratna Company (ONGC) as an Executive Engineer prior to 31 years in Institutes ( 8+1 Years in Indian Institute of Engineering Science and Technology(IIEST) and 22 Years in Jadavpur University) in different capacities. Direction for current time Technological Institutes “Research is the transformation of money into knowledge. Innovation is the transformation of knowledge into money” : Further Words of inspiration: Stand up, be hold, be strong. Take the whole responsibility on your own shoulders and know that you are the creator of your own destiny. -- Swami Vivekananda. "Have enough courage to start and enough heart to finish." – Jessica N. S. Yourko

48. That's End of Today’s Talk All Listeners! Thank You

49. Thank You .. Questions ?

50. Books : for VLSI Design CMOS Digital Integrated Circuits: S.M.Kang and Y.Leblebici . VLSI Design Techniques for Analog and Digital Circuits : R.L.Geiger , P.E.Allen and N.R.Strader . Digital Integrated Circuits: J.M. Rebaey . Introduction to Digital Systems : M.Ercegovac , T.Land and J.H. Moreno. Essential of VLSI Circuits and systems : Kamran Eshraghian , Douglas A Pucknrll and Sholeh Eshraghian Modern VLSI Design systems on Silicon : Wayne Wolf Nanoscale CMOS VLSI Circuits design for Manufacturability: Sandip Kundu and Aswin Sreedhar Introduction to VLSI systems – a logic, circuit and system Perspective : Ming – Bo Lin CMOS VLSI Design -- a circuit and system perspective: N. H. E. Weste and D Harris CMOS Circuit Design , Layout and simulation: R J Baker