PRE FINAL REVIEW for book chapter final.pptx

Review

1.   Design of Energy Efficient High- Speed 1- bit Hybrid Full adder for fast computation Presentation by V. Grace nissi 201FB11006 M.Tech 2nd year (VLSI design) Under the Guidance of Dr. Satyajeet Sahoo Ph.D Assistant Professor Dept . Of ECE Vignan’s Foundation for Science Technology and Research(deemed to be University )

2. COMMENTS Purpose of 8T XOR-XNOR Advantages of 8T XOR-XNOR Literature survey 8/20/2022 2

3. OUTLINE Objective Introduction Literature Review Proposed Work done References 8/20/2022 3

4. Objective To design a Novel Energy Efficient XOR-XNOR logic circuit with full swing output voltage. To implement a 1-bit Full Adder using XOR-XNOR. To verify the performance parameters such as power, Delay, power delay product, Energy delay product for 8-bit Parallel adder 8/20/2022 4

5. Introduction Power consumption and area reduction of logic and memory have become primary focuses of attention in VLSI digital design. To realize a full adder (FA) circuit, several static CMOS logic styles have been presented. These logic styles can be broadly classified into two categories: classical design style and hybrid design style. In classical design style, the FA is designed in a single module using MOS transistors. It provides full swing outputs and robustness against voltage scaling and transistor sizing. The main drawback of this circuit is high input capacitance as each of the input is connected to the gates having at least a pMOS and an nMOS transistor which degrades the speed of the adder. The main advantage of hybrid style is that all the modules can be optimized at the individual level, and the number of transistors can be reduced, which reduces the internal power dissipating nodes 8/20/2022 5

6. LITERATURE SURVEY Paper 1: High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell Performance parameters in terms of Power, delay, driving capability is largely dependent on the design of XOR-XNOR-cell. Advantages High speed operation Good driving capability Full swing output voltage. 8/20/2022 6

7. 8/20/2022 7 Fig. 1: Block Diagram of Hybrid logic Full adder © J.Kandpal,et.al.,“ High -Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell”, IEEE transactions on very large scale integration (VLSI) systems, 28,1413-1422,2020 .

8. 8/20/2022 8 Fig. 2: Existing Full adder Design © J.Kandpal,et.al.,“ High -Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell”, IEEE transactions on very large scale integration (VLSI) systems, 28,1413-1422,2020 .

9. Paper 2: Hamed Naseri and Somayeh Timarchi , “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 8, AUGUST 2018. Advantages : This work implemented an XOR/XNOR-cell design resulting in High Speed Low Power consumption Low Power delay-Product (PDP ) 8/20/2022 9

10. 8/20/2022 10 Fig. 1. (a) and (b) Full-swing XOR/XNOR circuits (c ) and (d) XOR–XNOR circuits © Hamed Naseri and Somayeh Timarchi , “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”- IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 26, NO. 8, August 2018.

11. 8/20/2022 11 (e) and (g) XOR–XNOR circuits © Hamed Naseri and Somayeh Timarchi , “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”- IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 26, NO. 8, August 2018.

12. Hybrid FA circuits 8/20/2022 12 © Hamed Naseri and Somayeh Timarchi , “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”- IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 26, NO. 8, August 2018.

13. Proposed 8T XOR-XNOR P4 N3 N4 N2 N1 P2 P3 P1 GND VDD XNOR XOR B A 8/20/2022 13

14. Truth table of XOR-XNOR XOR A B XOR 1 1 1 1 1 1 XNOR A B XOR 1 1 1 1 1 1 8/20/2022 14

15. Proposed 8T XOR-XNOR waveform 8/20/2022 15

16. Comparison Table- XOR/XNOR design XOR-XNOR CIRCUITS No. of Transistors Delay( ps ) Power ( μ W) PDP (10 -18 ) XOR XNOR Aguirre 12 51.6 54.9 7.01 450.79 Radhakrishnan 6 106 96.5 10.9 1144.4 Chang 10 93.8 68.8 10.8 1012.16 Valshani 10 74.7 50.2 10.7 730.59 Naseri 12 50.9 49.0 7.98 445.04 Existing base paper 10 46.3 47.4 7.89 428.16 Proposed 8 40.1 42.05 0.187 7.498 8/20/2022 16

17. Analysis of XOR/XNOR-circuit 8/20/2022 17

18. Module 3 Module 2 Module 1 Proposed 1-bit hybrid full adder CARRY C SUM C A B A XNOR XOR P7 P6 P5 P4 P3 P2 P1 P8 N7 N8 N5 N4 N2 N1 N3 N6 8/20/2022 18

19. Proposed hybrid full adder wave form 8/20/2022 19

20. Comparison Table for 1- bit HFA Designs Average Power uW Delay ( μ s) EDP (Js) Transistor count C-CMOS 2.568 1.55 6.169 28 Mirror 2.523 1.534 5.937 28 CPL 6.236 1.44 12.93 32 TFA 2.98 1.285 4.92 16 TGA 3.277 1.213 4.821 20 16T-Hybrid 2.506 0.978 2.397 16 10T 2.34 5.95 82.84 10 GDI 1.665 3.3 18.131 10 Existing 3.053 0.344 0.361 14 Proposed 0.644 0.0526 0.0017 16 8/20/2022 20

21. Analysis of 1- bit HFA 8/20/2022 21

22. 8-bit Ripple carry adder Carry S7 S6 S5 S3 S4 S2 S1 S0 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a1 b1 a0 b0 Gnd 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 1bit Hybrid full adder Carry Sum A B Cin 8/20/2022 22

23. 8-bit Ripple carry adder wave form 8/20/2022 23

24. Work done Proposed 8T XOR-XNOR circuit Proposed 1-bit Hybrid full adder circuit Designed 8-bit Ripple carry adder by using proposed XOR-XNOR Compared the Proposed XOR-XNOR, 1-bit HFA with existing designs and calculated delay, power, power delay product . 8/20/2022 24

25. REFERENCES Ayush Kumar, Ankit Kumar Dr. Deva Nand "Design and Study of Dadda Multiplier by using 4:2Compressors and Parallel Prefix Adders for VLSI Circuit Designs" 2021 2nd International Conference for Emerging Technology (INCET)Belgaum, India. May 21-23, 2021. Garima Thakur , Harsh Sohal,Shruti Jain "Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications"2020 International Conference on Computational Performance Evaluation ( ComPE )North-Eastern Hill University, Shillong , Meghalaya, India. Jul 2-4, 2020. J.Kandpal,et.al.,“ High -Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell”, IEEE transactions on very large scale integration (VLSI) systems, 28,1413-1422, 2020 . 8/20/2022 25

26. Continued.... Mehedi Hasan , Md. Jobayer Hossein , Mainul Hossain , Hasan U. Zaman and Sharnali Islam-“ Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation”- IEEE Trans. Very Large Scale Integr . (VLSI) Syst., Vol. 67, no. 8, pp-1464-1468 , August 2020 . Hamed Naseri and Somayeh Timarchi , “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates”- IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 26, NO. 8, August 2018 . Samraj Daphni , Kasinadar Sundari Vijula Grace "Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications"- Advances in Science, Technology and Engineering Systems Journal Vol. 4, No. 2, 102-106 (2019)  S. Wairya , R. K. Nagaria , and S. Tiwari , “New design methodologies for high-speed low-voltage 1-bit CMOS Full Adder circuits,” Int. J. Computer Technology . Appl., vol. 2, no. 2, pp. 190–198, 2011 . 8/20/2022 26

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