project ppt (1)FINAL vlsi_field_gate.ppt

VLSI

1. FPGA Hardware Implementation
of 2D-DWT Using Systolic Array
Architecture in VLSI
Mentor : PROF. MRUGENDRA VASMATKAR
Group number : A17
Anuradha Chopade(11)
Bhagyashree Kudtarkar(36)
Karuna Lakhani(38)
Renuka More(43)

2. What is wavelets?
• Wavelets(little wave) are functions that are concentrated in
time as well as in frequency arround a certain point
•Visualized as a "brief oscillation"

3. Why Wavelet Transform
•Wavelet transform is most appropriate for non-stationary signals
•The basis function vary both in frequency range and spatial
range
•Good frequency resolution for low frequency component
•High temporal resolution for high frequency component

4. Discrete Wavelet Transform
•The discrete wavelet transform (DWT) is an
implementation of the wavelet transform using a discrete
set of the wavelet scales and translations obeying some
defined rules
•This transform decomposes the signal into mutually
orthogonal set of wavelets

5. Wavelet Transforms in Two
Dimensions
•The two-dimensional DWT can be implemented using digital
filters and down sample.
•Three sets of detail coefficients including the horizontal,
vertical, and diagonal details are produced and also we get
a approximation output
•This is achieved by using filter bank

6. Original
Image
Horizontal
Approximati
on
Horizontal
Detail
Approximat
e Image(LL)
Vertical
Detail(LH)
Horizontal
Detail(HL)
Diagonal
Detail(HH)
Low pass
Filter on
rows
High
pass
Filter on
rows
Low pass
Filter on
Columns
High pass
Filter on
Columns
Low pass
Filter on
Columns
High pass
Filter on
Columns

7. DWT along rows and columns
2-Level Dwt

8. Block diagram of 2d-DWT
8

9. Filter banks and Sub-band coding
•This decomposition is
repeated to increase the
frequency resolution .
•In signal processing, Sub-
band coding (SBC) is any
form of transform
coding that breaks a signal
into a number of different
frequency bands and
encodes each one
independently.
Splitting an signal spectrum with an filter bank
A 3 level DWT

10. Systolic array
Pipelined arrangement of
cells
Data processing units(Systolic
Cells)
Input and data flow through
the array
Parallel computing
The arrangement of such
arrays can be utilized to
implement linear, circular
convolution and other to
implement other applications

12. Flow graph
2D -Input image
Resize to 256 to 256
DWT process using
HDL programming
Integrating the lpf
and hpf values for
DWT process
Reshaping values
into image
Output image
Matlab
program
VHDL
programmi
ng
Matlab program

13. SA-DWT Architecture

14. 1.Filter unit
The filter unit proposed for this architecture is a six tap digital
filter, whose transfer function is given by the equation,
H(z)=g(0)+g(1)z-1+g(2)z-2+g(3)z-3+g(4)z-4+g(5)z-5

1(a)
L(z)=h(0)+h(1)z-1+h(2)z-2+h(3)z-3+h(4)z-4+h(5)z-5
1(b)
Where H(n) is the sixth order high pass transfer function, L(n) is
the sixth order low pass transfer function, g(0)-g(5) and h(0)-h(5)
are the coefficients of the HPF and LPF.

15. 2.Storage unit
Input Delay unit
Register bank
 Input Register Bank
(RBI).
 Low-pass Register Bank
(RBL).
 High-pass Register Bank
(RBH.

16. 3.Control unit
The CU is a switch that directs data
from the input and low-pass register
bank to the filter unit.
The CU is the modular switch with a
number of subcomponents equal to
the number of taps in the filter unit.
The CU multiplexes data from input
register bank for every second cycle,
and from low-pass register bank in
cycles 4, 6 and 8.
In cycle 2 the CU remains ideal, i.e.,
it dose not allow any passage of data.
The complete synchronization is
controlled by the 2 select inputs to the
multiplexer.

17. RESULT AND IMPLEMENTATION

18. RESULT OF 1-D DWT

19. RESULT OF 2-D DWT

20. RTL SCHEMATIC

21. RTL schematic of Storage Unit

22. RTL schematic of filter unit

23. RTL schematic of control unit

24. “
”
RTL schematic of delay unit

25. RTL of 2-D DWT architecture

26. RTL of 2-D DWT Architecture with output
RAM

27. RTL SCHEMATIC

28. Simulation Results
SA-DWT Simulation

29. DWT Synthesis Result
 This device utilization includes the following.

30. Future Work

31. Speech Processing:
Wavelets also find application in speech compression, which
reduces transmission time in mobile applications. They are used in
denoising, edge detection, feature extraction, speech recognition,
echo cancellation and others. They are very promising for real
time audio and video compression applications. Wavelets also
have numerous applications in digital communications.
Orthogonal Frequency Division Multiplexing (OFDM) is one of
them. Wavelets are used in biomedical imaging. The popularity of
Wavelet Transform is growing because of its ability to reduce
distortion in the reconstructed signal while retaining all the
significant features present in the signal.

32. Conclusion
A systolic VLSI architecture for computing Two dimensional DWT in has been
presented
The main objective of the proposed DWT-SA architecture is to develop a design
resource for designers to implement systolic array architecture of DWT for various
wavelets according to the design need such as clock speed, area and time.
Systolic array architecture has efficient hardware utilization and it works with data
streams of arbitrary size. The design is cascadable, for computation of one, two and
three decomposition level. This architecture computes N coefficients in N clock
cycles and achieves real time operation by executing computations of higher octave
coefficients in between the first octave coefficient computations
The implementation employs only one multiplier per filter cell, and hence results in
a considerably smaller chip area.
The DWT-SA architecture does not use any external or internal memory modules to
store the intermediate results and therefore avoids the delays caused by access,
read, write and refresh timing. But when cascading it to 2D-DWT it uses one
transpose memory for converting rows into columns.
The architecture was be simulated in VLSI and has high hardware utilization
efficiency than the referred. By performing the synthesis to the design using Xilinx
ISE the minimum delay of architecture is found to be 6.92 ns.

33. References
1.Daubechies, “Orthonormal bases of compactly supported wavelets,” Comm. Pure Appl. Math, Vol. 41, pp. 906-966,
1988.
2.S. G. Mallat, “A theory of multiresolution signal decomposition: the wavelet representation,” IEEE Trans. on
Pattern Recognition and Machine Intelligence, Vol. 11, No. 7, July 1989.
3.M. Vetterli and C. Harley, “Wavelets and filter banks: theory and design,” IEEE Transactions on Signal processing,
Vol. 40, No. 9, pp. 2207-2232, 1992.
4.Y. Meyer, Wavelets: Algorithms and Applications, SIAM, Philadelphia, 1993
5.R. A. Devore, B. Jawerth and B. J. Lacier, “Image compression through wavelet coding,” IEEE Trans. on
Information Theory, Vol. 38 .
6.O. Rioul and M. Vetterli, “Wavelets and signal processing,” IEEE Signal processing Magazine, pp. 14-38, Oct.
1991.
7.R. A. Gopinath, Wavelets and Filter Banks – New Results and Applications, PhD Dissertation, Rice University,
Houston, Texas, 1993.
8.S. G. Mallat, "Multifrequency channel decompositions of images and wavelet models", IEEE Trans. On Acoustics,
Speech and Signal Processing Vol. 37, No. 12, pp. 2091-2110, Sept. 1989.
9.K. K. Parhi and T. Nishitani, “VLSI architectures for discrete wavelet transforms”, IEEE Trans. On VLSI Systems,
pp. 191-202, June 1993.
10.Aware Wavelet Transform Processor (WTP) Preliminary, Aware Inc., Cambridge, MA.