Synchronous down counter

Synchronous down counter with full description.
All the flip-flop are clocked simultaneously.
Synchronous counters can operate at much higher frequencies than asynchronous counters.
As clock is simultaneously given to all flip-flops there is no problem of propagation delay. Hence they are high speed counters and are preferred when number of flip-flops increase's in the given design.
In this counter will counter

1. GYANMANJARI INSTITUTE OF TECHNOLOGY

2. Prepared by: Ronak Sutariya Enrolment No: 151290107052 Branch: Computer Engineering Subject: Digital Electronics (2131004) Topic: Synchronous Down Counter

3. Index No. Title 1 Introduction of Counter 2 Synchronous Counter 3 Steps 1 to 7 4 2-Bit Synchronous Down Counter 5 3-Bit Synchronous Down Counter 6 Application Synchronous Down Counter

4. A counter is a sequential circuit that goes through a predetermined sequence of states upon the application of clock pulses. Counters are categorized as: Synchronous Counter: All FFs receive the common clock pulse, and the change of state is determined from the present state. Ripple(Asynchronous) Counters: The FF output transition serves as a source for triggering other FFs. No common clock. Counters

5. All the flip-flop are clocked simultaneously. Synchronous counters can operate at much higher frequencies than asynchronous counters . As clock is simultaneously given to all flip-flops there is no problem of propagation delay. Hence they are high speed counters and are preferred when number of flip-flops increase's in the given design. In this counter will counter Synchronous Down Counter

6. Step 1: Determine the number of flip-flop needed. Step 2: Type of flip-flop to be used. Step 3: Write the excitation table for the flip-flop. Step 4: Determine the state diagram . Step 5:Make excitation table for the counter . Step 6: K-map simplification. Step 7: Draw the logic diagram. Step 1 To 7

7. Step 1: Flip-flops required are N Here N=4 so No of flip-flop is required is 2. Step 2: Here we will us JK flip-flops. Step 3: Excitation table for the JK flip-flop   J K X 1 1 X 1 X 1 1 1 X J K X 1 1 X 1 X 1 1 1 X 2-Bit(MOD-4) Synchronous Down Counter

8. Step: 4 State Diagram

9. Step: 5 Excitation table for the 2-bit down counter . Present state Next state Flip-Flop input 1 1 1 X 1 X 1 X X 1 1 1 X 1 1 X 1 1 1 X X 1 Present state Next state Flip-Flop input 1 1 1 X 1 X 1 X X 1 1 1 X 1 1 X 1 1 1 X X 1

10. Step: 6 K-map simplification.

11. Step: 7 Draw the logic diagram.

12. Step 1: Flip-flops required are N Here N=8 so No of flip-flop is required is 3. Step 2: Here we will us T flip-flops. Step 3: Excitation table for the T flip-flop   T 1 1 1 1 1 1 T 1 1 1 1 1 1 3-Bit(MOD-8) Synchronous Down Counter

13. Step: 4 State Diagram

14. Step: 5 Excitation table for the 3-bit down counter . Present state Next state Flip-Flop input 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Present state Next state Flip-Flop input 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15. Step: 6 K-map simplification.

16. Step: 7 Draw the logic diagram.

17. Thank You.