Transistor logic of vlsi subject for ece .pptx

this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year
this presentation deals with the subject of very large scale integrated circuits it is very useful for ece students of 3rd year

1. Pass Transistor

2. I ntroduction : The Pass Transistor concept is based on the use of relay switches. A number of inputs are connected to switches and only one of the switches is chosen to be transferred to the output. In essence, we have created a Multiplexer

3. Cont …. MOSFET Acts as Switch OFF cut-off Region when < ON Linear(or) Saturation Region when > MOSFET ON-OFF conditions are used as “Switch” Pass Transistor uses a n MOS or p MOS Transistor to transfer charge from input node to output node ,under the control of gate voltage. the output remains in high impedance state when voltage is Zero. The process of transferring the charge from the input node to the output under the control of gate voltage is called charge steering.  

4. Cont… nMOS pass transistor The n MOS transistor as shown in figure n MOS turns “ON” for high input at the gate terminal and produces “strong 0” at the drain output. nMOS transistor pass a strong 0 but a weak 1

5. Cont ….. P MOS Pass transistor The p MOS transistor as shown in figure p MOS turns “ON” for low input at the gate terminal and produces “strong 1” at the drain output. p MOS transistor pass a weak 0 but a strong 1

6. Cont …. Realization of logic gates using pass transistor logic(PTL) (1).Design of 2 input AND gate using PTL. (2).Design of 2 input OR gate using PTL.

7. Cont … 3.Design of 2 input XOR gate using PTL. It is an array of MOS transistor which are connected in series and passes /carries logic levels. For example below is a pass transistor which implement ‘AND’ opearion and passes logic ‘1’information

8. nMOS Inverter

9. Introduction: Generally inverters are basic components for fabricating large circuits. In circuit if we consider logic ‘1’ means High voltage VDD logic ‘0’ means low voltage ground (0 volts) Voltage transfer characteristics of ideal inverter as shown in figure

10. nMOS Inverter: nMOS inverter with resistive load circuit as shown in figure This basic inverter requires a transistor with ‘source’ Connected to ground and drain connected to load ‘ ’ Via a load resistor. Here the resistor act as pull up device and N MOS Device act as pull-down device. When =0v,E-NMOSFET is OFF but there is a conducting path (short circuit path)Between and = (ii)When = . E-NMOSFET is ON and there is a Conducting path between and ground. = - But fabrication of resistor on ‘ si ’ substrate is not Convenient because it occupies large substrate area and results in large amount of power dissipation.  

11. Cont … So to solve this problem we use FETS as loads to drive invertors . When =0v,E-NMOSFET is OFF but there is a conducting path (short circuit path)Between and = (ii)When = . E-NMOSFET is ON and there is a Conducting path between and ground. = - If input is lower voltage (logic 0 )then inversion layer not get formed, so drain current will be zero If input is higher voltage(Logic 1),then inversion layer will get formed, so drain current will increses,which will decreases output to logic 0  

12. Cont …. Voltage transfer characteristics of nMOS invertor as shown in figure If input is lower voltage (logic 0) then inversion layer not get formed, so drain current will be zero If input is higher voltage(Logic 1),then inversion layer will get formed, so drain current will increses,which will decreases output to logic 0 = -  

13. Cont.…. The vs vin NMOS transfer characteristics are shown below Note that whenever vin of E-NMOS exceeds its , decreases. Gain = = =- Gain =- We know that = | =constant We know that = = . The point at which = is denoted as . The point and transfer characteristics can be shifted by variation of  

14. Determination of pull-up to pull-down ratio( ) for NMOS inverter driven by another NMOS inverter  

15. Introduction : Consider arrangement as shown below in which an inverter driven from the output of another similar inverter. When cascading logic devices care must be taken to preserve integrity of logic levels i.e design circuit so that = = Depletion mode transistor =0v under all conditions  

16. Cont …. Depletion NMOS as a load and enhancement mode NMOS as a driver i.e NMOS inverter . Assume equal margins around inverter: = = =0.5 Both transistor of NMOS inverter are in saturation For depletion mode transistor =0v, =  

17. Cont …. ……………….(1) For enhancement mode transistor = ……..(2) Since currents are equal then = [convention Z= ] . = . -  

18. Cont …. Substitute in typical values =0.2 , =-0.6 , 0.5 0.2+ =2 = An inverter driven from the output of another should have a ratio of  

19. Determination of pull-up to pull-down ratio for an NMOS inverter driven through one or more pass transistor

20. Determination of pull-up to pull-down ratio for an NMOS inverter driven through one or more pass transistor It is often the case that two inverters are connected via series of switches(pass transistors) We are connected that connection of transistors in series will degrade the logic levels into inverter 2 Consider the arrangement shown below. all pass transistor gates connected to so there is a loss of i.e vin2= - ( =pass transistor )  

21. Cont …. With input if it is at then pull-down transistor is conducting but with a low voltage across it. It is in its resistive region represented by . mean while the pull-up transistor is in saturation and is represented by current source.  

22. Cont … Consider inverter 1: Case1 :pull up Transistor ,it is a D-NMOSFET where vgs=0 so it is operated directly in saturation region. For depletion mode transistor =0v, = ……………….(1) Case 2: Pull down Transistor ,it is a E-NMOSFET where Input= first operated in resistive region where < -  

23. Cont … ( - ) - ] = Note: is small so ignore = …….(2) The output of the inverter 1 i.e equations (1) and (2) sub in below equation = . = . = . ………(3)  

24. Cont ….. Consider inverter 2: Case1 :pull up Transistor ,it is a D-NMOSFET where vgs=0 so it is operated directly in saturation region. For depletion mode transistor =0v, = ……………….(4) Case 2: Pull down Transistor ,it is a E-NMOSFET where Input= - first operated in resistive region where < -  

25. Cont … ( - ) - ] But = - ( - - ) - ] = Note: is small so ignore = …….(5) The output of the inverter 1 i.e equations (4) and (5) sub in below equation = . = .  

26. Cont … = . = . . ……(6) . = . . = Typical values =0.2 and = 0.3 = =  

27. Cont … = = (1.6)= (2) = (2) = An inverter driven through one or more pass transistor should have ratio of  

28. CMOS Inverter

29. Introduction: Case(1) when NMOS Transistor is OFF PMOS Transistor is ON And there is conducting path between and Case(2) when NMOS Transistor is ON PMOS Transistor is OFF And there is conducting path between and ground. We have seen that ,the current /voltage relation ships for the the MOSFET may Be written as in Linear region [( )- ]  

30. Cont … in saturation Region In both case ‘k’ is a technology dependent parameter such that k= The factor contributes by the geometry of the MOSFET.so in common practice we write β =k = . Where ‘ β ’ for both NMOSFET,PMOSFET are follows = . = . s  

31. Cont …. The CMOS Inverter has ‘5’Different Regions of operation Region 1 :this is the region at which =0 (logic 0) NMOS Transistor is OFF PMOS Transistor is ON = (logic1) Region 5: this is the region at which = (logic 1) NMOS Transistor is ON PMOS Transistor is OFF = (logic0)  

32. Cont … Region 2 :In this region the input voltage has increased to a level which just more than the threshold voltage of mosfet . The N-MOSFET conducts and has a large voltage between source and drain.so it is in saturation and acts as current source. The P-MOSFET also conducts but with only a small voltage across it. and is operated in resistive region .

33. Cont …. A small current now flows through the inverter from to Region 4. This is similar to region2 but the roles of ‘PMOSFET’ and MOSFET’ are reversed . Small currents flows through inverter from to ground.  

34. Cont … Region 3. this is the region at which both MOSFTs are in saturation. The currents in each FET must be same since FETS are in series so =  

35. Cont …. Where = , = We know that = . =- . = + = + n = ………………………(1)  

36. Cont …. But in this region both FETs are in saturation acts as two current sources in series results in unstable condition. A change over from one logic level to other logic level is rapid in this region. If = and = - after substituting in eq (1) = At = a changeover will occur between the logic levels and symmetrical about the point at which = this is only the point at which two β factors are equal. = . = . = [ =1250 , =480 ] =2.5  

37. BiCMOS Inverter Operation Vin =0 V , T4 is OFF so that T2 will be non-conducting But T3 is ON and supplies current to the base of T1 which will conduct and act as a current source to charge the load CL toward VDD . The output of the inverter will rise to VDD less the base to emitter voltage VBE of T1. Vin =VDD V , T3 is OFF so that T1 will be non-conducting But T4 is ON and supplies current to the base of T2 which will conduct and act as a current sink to discharge the load CL toward 0 v . The output of the inverter will fall to 0 v plus the collector to emitter voltage VCE of T2. T1 and T2 will present low impedances when turned on into saturation and the load CL wiil be charge or discharges rapidly. Inverter1

38. The output logic levels will be good and will be close to the rail voltages since VCEsat is quite small and VBE= 0.7 volts. The inverter has a high input impedance and low output impedance. The inverter has high current drive capability but occupies a relatively small area and have high noise margins. inverter2

39. Final BiCMOS Inverter

40. CMOS Inverter Cross-Sectional view with Latch-up circuit

41. Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply (V DD ) and the ground (GND) due to the interaction of parasitic PNP and NPN bipolar junction transistors (BJTs). These BJTs form a silicon – controlled rectifier (SCR) with positive feedback and virtually short circuit V DD to the ground, thus causing excessive current flows and even permanent device damage . Latch-up occurs when: When both BJTs conduct, creating low resistance path between V DD and GND . Product of gain of two transistors in the feedback loop is greater than one (β 1 x β 2 ≥ 1)

42. In the equivalent circuit : Q1:   vertical bipolar PNP transistor whose base is formed by the n-well with its base-to-collector current gain (β 1 ) as high as several hundred. It is associated with pMOS . Q2: lateral bipolar NPN transistor whose base is formed by the p-type substrate with its base-to-collector current gain (β 2 ) ranging from few tenths to tens. It is associated with nMOS . R well :   the parasitic resistance in the n-well structure with its value ranging up to 20kΩ . R sub :   substrate resistance that strongly depends on the substrate structure with its value ranging from several hundred to few ohms. Latch-up Circuit model

43. BiCMOS Latch-up Susceptibility A reduction of substrate resistance. A reduction of N-well resistance. A reduction in both resistances means that a large lateral current is necessary to invite latch-up and a higher value of holding current is also required. The parasitic ( pnp ) transistor which is part of the n-well latch circuit has its beta reduced owing to the presence of n+ buried layer. This has the effect of reducing carrier life time in the n-base region and this contributes the reduction in beta.